Why Attend?

International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

Synopsys' Virtual Experience

Synopsys Virtual Booth Hours

Tuesday, November 3rd
11:00 - 11:30 a.m.; 12:30 - 1:00 p.m.; 2:00 - 2:30 p.m.

Wednesday, November 4th
11:00 - 11:30 a.m.; 12:30 - 1:00 p.m.; 2:00 - 2:30 p.m.

Thursday, November 5th
11:00 - 11:30 a.m.; 12:30 - 1:00 p.m.; 2:00 - 2:30 p.m.

*All time are listed in Eastern Standard Time

Tuesday, November 3rd

11:00 - 11:30 a.m. EST -  TestMAX Overview – Shift-left DFT for high, quality efficient test

12:30 - 1:00 p.m. EST -  Fault simulation for manufacturing and highly reliable designs

2:00 - 2:30 p.m. EST - TestMAX Overview – Shift-left DFT for high, quality efficient test

 

Wednesday, November 4th

11:00 - 11:30 a.m. EST -  Fault simulation for manufacturing and highly reliable designs

12:00 - 12:30 p.m. EST - Memory Test & Repair and Hierarchical Test for PHY IP targeting Automotive SoCs

2:00 - 2:30 p.m. EST - TestMAX Overview – Shift-left DFT for high, quality efficient test

 

Thursday, November 5th

11:00 - 11:30 a.m. EST -  Memory Test & Repair and Hierarchical Test for PHY IP targeting Automotive SoCs

12:30 - 1:00 p.m. EST -  TestMAX FuSa – Fast, comprehensive functional safety analysis for ISO 26262

2:00 - 2:30 p.m. EST - Fault simulation for manufacturing and highly reliable designs

Don McMillan
Former engineer turned comedian

Don't miss your opportunity to see funny man and leading industry comedian, Dan McMillian at our networking event.

Join us in our virtual booth and provide your contact information to receive an invitation to one of three live virtual shows:

• November 3rd at 5:30 p.m. EST
• November 4th at 5:30 p.m. EST
• November 5th at 5:30 p.m. EST

Monday, November 2nd

10:00 a.m. EST

Advances in FinFet Memory Test & Repair for Complex SOCs

Yervant Zorian, Synopsys

Recent growth in artificial intelligence and large content delivery applications have led to an explosion in the utilization of memories, including on-chip embedded memories and off-chip high-bandwidth memories. This tutorial will start with the trends and challenges of growing memory utilization in SOCs and then discuss how to meet test and repair requirements for today's defects in advanced technology nodes, down to 4nm. These include FinFET, aging, reliability, process variation failures, which occur in manufacturing flow and during semiconductor lifecycle. The tutorial will cover the BIST and Repair solutions to address debug, diagnosis, yield optimization, and data retention. Given the tens of thousands of embedded memory instances in today's SOCs, it will also cover the memory BIST architectural trade-offs, power management constraints, timing implications, test scheduling optimization, and area minimization options

2:00 p.m. EST

Automotive Safety, Reliability & Test Strategies

Yervant Zorian, Synopsys

Given today's fast-growing automotive semiconductor industry, this tutorial will discuss the implications of automotive quality, functional safety, and reliability on all aspects of automotive SOC lifecycle, while accelerating time to market for these semiconductor ICs. The automotive SOC lifecycle stages will include design, silicon bring-up, volume production, and particularly in-system operation. Today's automotive safety-critical chips need multiple in-system modes, such as power-on and power-off self-test and repair (key-on/key-off), periodic in-field self-test during mission mode, advanced error correction solutions, etc. This tutorial will analyze these specific in-system test modes and discuss the benefits of using ISO 26262 including its second edition, and several newer standardization efforts, in order to ensure that standardized functional safety requirements are met.

Tuesday, November 3rd

1:00 p.m. EST

Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications

Gurgen Harutyunyan, Synopsys

In this paper, die-to-die testing scenario is considered, and a methodology is described for mitigating the effects of errors by using well-known Error Correcting Codes (ECC). An advanced ECC solution is then presented along with the infrastructure needed for effectively testing DRAMs, including soft errors and permanent faults.

3:30 p.m. EST

Panel - Chiplet and Test Trends

Yervant Zorian, Synopsys

Coming soon.

Thursday, November 5th

1:00 p.m. EST

Test and Diagnosis Solution for Functional Safety

Gurgen Harutyunyan, Synopsys , Yervant Zorian, Synopsys

and Marco Casarsa, STMicroelectronics

This paper discusses the automotive requirements of ISO 26262 standard and its implication on conventional test and diagnosis flows. It presents a safety-oriented manufacturing test and diagnosis solution meeting automotive system-on-chip (SoC) requirements. The implementation details, automotive features and experimental results are described showing the effectiveness of the proposed solution

5:00 - 6:30 p.m. EST

IEEE Automotive Reliability and Test Workshop 2020

Corporate Supporter: Synopsys

The ART workshop focuses exclusively on test and reliability of automotive and mission-critical electronics, including design, manufacturing, burn-in, system-level integration and in-field test, diagnosis and repair solutions, as well as architectures and methods for reliable and safe operations under different environmental conditions. With increasing system complexity, security, stringent runtime requirements for functional safety, and cost constraints of a mass market, the reliable operation of electronics in safety-critical domains is still a major challenge. This edition of the ART Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.

5:00 - 6:30 p.m. EST

Seventh IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST

Corporate Supporter: Synopsys

The 3DC-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional, chiplet-based, and stacked ICs (3D-SICs), including systems-in-package (SiP), package-on-package (PoP), 3D-SICs based on through-silicon vias (TSVs), micro-bumps, and/or interposers. While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing such products. The 3DC-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. 3DC-TEST will take place in conjunction with the IEEE International Test Conference (ITC) 2020.

Friday, November 6th

All day

IEEE Automotive Reliability and Test Workshop 2020

Corporate Supporter: Synopsys

The ART workshop focuses exclusively on test and reliability of automotive and mission-critical electronics, including design, manufacturing, burn-in, system-level integration and in-field test, diagnosis and repair solutions, as well as architectures and methods for reliable and safe operations under different environmental conditions. With increasing system complexity, security, stringent runtime requirements for functional safety, and cost constraints of a mass market, the reliable operation of electronics in safety-critical domains is still a major challenge. This edition of the ART Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.

All day

Seventh IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST

Corporate Supporter: Synopsys

The 3DC-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional, chiplet-based, and stacked ICs (3D-SICs), including systems-in-package (SiP), package-on-package (PoP), 3D-SICs based on through-silicon vias (TSVs), micro-bumps, and/or interposers. While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing such products. The 3DC-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. 3DC-TEST will take place in conjunction with the IEEE International Test Conference (ITC) 2020.