The IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, applications, hot topics and new trends in the area of electronic-based circuits and system testing, reliability, security and validation.
Friday, May 28, 2021
18:30 – 19:10: Keynote: A perspective on 1500 History - Yervant Zorian
19:10 – 19:30: Invited paper presentation: Update on 1500 - Mike Ricchetti
19:30 – 19:50: Invited paper presentation: End-to-End Automation with Robust, Standards-Based Access
Bala Tarun Nelapatla and Adam Cron
The 1st International Test Access, Automation and Adoption (TAAA) aims to be a focused and open platform dedicated for exchanging insights on the three A’s: Access, Automation and Adoption. The scope of the workshop is to address challenges on the path from pure research-oriented works to solutions that can be practically applicable in industry. The areas of interest include (but are not limited to) various aspects in relation to test access, automation and adoption in respect to existing standards, like IEEE Std. 1149.x, 1500, 1581, 1687, and 1838, and to on-going standardisation work, like P1687.1 , P2654 , P2929, P1149.4, P1450, P1450.1, P1450.6.
May 28, 2021
18:30 - 19:30 *UTC+2
Panel: Test and dependability for AI chips: any different from traditional chips?
Moderator: Mehdi Tahoori, KIT, Germany
Alberto Bosio, INL, Ecole Centrale de Lyon, France
Siddharth Garg, NYU, USA
Yiorgos Makris, Univ. Texas at Dallas, USA
Fadi Maamari, Synopsys, USA
Eric Zhang, Horizon, Canada
Recent advances in Artificial Intelligence (AI), in particular deep learning, have led to numerous applications, including computer vision, speech recognition, natural language processing, robotics, etc. Autonomous vehicles are also afoot and AI will be the core enabling technology. In parallel, there is intense activity in designing dedicated hardware for AI. On one hand, AI hardware accelerators are demanded to support the tremendous processing power, unprecedented speed, and memory costs that deep neural networks require so as to realize their full potential. On the other hand, there is a large incentive for moving the AI algorithms execution from the cloud into the edge devices, i.e. Internet-of-Things (IoT) devices, in particular for meeting data confidentiality and network bandwidth requirements and eliminating the communication latency. Edge devices are expected to include local AI processing, yet this is challenging as an edge device is a resource-constrained environment. AI hardware design efforts rapidly evolve exploring various architectures (e.g., machine learning-based, spiking), design flavors (e.g., digital, mixed analog-digital), and emerging technologies (e.g., memristive devices arranged into crossbars to implement efficiently the multiply-add matrix operations in neural networks).
Visit Synopsys virtual booth where we will be available to discuss our solutions and answer any questions.
Virtual Booth Hours:
*All times are noted for UTC+2