Synopsys Timing Constraints Manager

Best-in-Class, No-Noise SDC Verification and Management Solution to Significantly Boost Productivity of Electronic Design Teams

Synopsys Timing Constraints Manager, built on FishTail Design Automation Golden Timing Constraints, offers a unique approach to improving the chip design process by automatically generating and verifying golden timing constraints early in the design cycle. Synopsys Timing Constraints Manager is a complete solution for the management of design constraints as chip-implementation progresses. Synopsys Timing Constraints Manager allow designers to drive chip-implementation with complete constraints that are formally proven to be correct and to then manage the constraints as chip-implementation progresses. The result is improved chip timing, area and power, and a shorter chip-implementation schedule with much fewer back-end timing closure iterations. Also, by formally proving the correctness of design constraints using Synopsys Timing Constraints Manager, design projects eliminate the risk of silicon failure resulting from incorrect timing exceptions.

Synopsys Timing Constraints Manager breakthrough, patented technology provides the ability to take a large, complex RTL or gate-level design and automatically abstract the behavior and structure of the design, so as to only keep the information that is required for the task being performed. The abstraction capability allows Synopsys Timing Constraints Manager to generate and verify timing exceptions on multi-million gate designs in an overnight run.

Key Benefits

Golden Timing Constraints
No noise SDC verification solution delivers superior quality of results by flagging only real issues
Automated & Easy to Use
Highly automated, configurable, and easy to deploy, does not require extensive training
Robust Technology for Tough Problems
Comprehensive timing exception, glitch verification, equivalence checking and mode-merging solutions

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Synopsys Acquires FishTail Design Automation, Unifying Constraints Handling for Enhanced Chip Design Process

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