Advanced Vector Translation

VTRAN® is a vector translation program that reads the state/time information from simulation or ATPG data files, performs optional processing on this data then re-formats it for any of over 30 popular logic simulators and testers. The program addresses the general class of problems involving simulation stimulus/result re-formatting encountered by designers who must navigate more than one logic simulation environment. A collection of test options for VTRAN also provide interfaces to many popular device testers, offering a direct path from logic simulation/ATPG vectors to test programs.


  • Re-formatting existing simulation data files generated by one simulator into files compatible with another simulator
  • Translating state data files from logic analyzers, test programs or other data sources into stimulus files compatible with logic simulators, including the incorporation of pin timing
  • Modifying simulation data files, including changing pin lists, pin order, bus radixes, time offsets, pin timing and time scaling
  • Translating simulation/ATPG output vector data or test programs into testbench data files for Verilog/VHDL resimulation and verification
  • Vector translation from simulation or ATPG-generated vectors into functional test vectors for physical device testers
  • Acts as a front-end to graphical waveform tools, enabling them to read and display nearly any vector data file

Data Readers

VTRAN reads data files from simulators, or other sources, using one of two methods. For some of the more popular simulators, VTRAN has canned readers that know how to read the time/state information of those files. Canned readers are currently available for the following file formats:

  • Verilog VCD (and eVCD) files
  • Popular ASIC vendor formats
  • Multiple simulation formats
  • Industry test formats, including WGL and STIL
  • Leading ATE vendor formats, including Advantest, Teradyne, Credence and IMS