Achieving Best Quality RTL for Faster Design Closure with RTL Architect

Wednesday, May 19, 2021                                                                                10:00 a.m. - 11:30 a.m. IST

Why Attend

This virtual event will present on a unique methodology to achieve better PPA for your design at an early RTL stage. 

Key highlights of this session will be focusing on:

  • Do you want to get a fast insight into the key RTL quality metrics? 
  • Do you want to get a more accurate power trend of your RTL?
  • Do you want to know how your RTL will behave in the downstream tools (physical implementation)? 
  • Get to hear first-hand experience from end users.

 

Who Should Attend?

This webinar is designed mainly for RTL architects, designers, and integrators who work on the front-end flow. 

 

Save Your Spot!

Agenda

10:00 - 10:10 a.m. IST

Welcome and Keynote Address

- Arvind Narayanan, Synopsys

10:10 - 10:40 a.m. IST

RTL Architect for Faster Design Closure

- Jim Schultz, Synopsys

10:40 - 11:00 a.m. IST

Tool Demo - RTL Architect

- Synopsys

11:00 - 11:25 a.m. IST

User Testimonial                                                                                      Case Study: Optimize and Configure Synopsys DesignWare IP with    RTL Architect

- Fergus Casey, Synopsys

11:25 - 11:30 a.m. IST

Q&A and Closing Remarks