Design Compiler Customer Quotes

May 31, 2016
“Design Compiler Graphical enables our design team to identify and remove routing congestion early in the flow and, with physical guidance to IC Compiler II, it enables us to speed up the critical physical place-and-route and final design closure phases.”
Pavel Vilk, engineering director at Avnet ASIC Israel, Ltd            

Sep 09, 2015
“Design Compiler Graphical's significant area and routing congestion reduction, combined with IC Compiler for place and route, enable our design teams to achieve faster timing and smaller area.”
Tatsuji Kagatani, manager of Design Automation Department at Renesas System Design Co., Ltd.

Jul 06, 2015
“With Design Compiler Graphical we can identify and fix timing issues in a timely manner during synthesis and achieve higher frequency and smaller area faster.”
Meisie Jong, general manager of Key ASIC's Technology Services

Nov 18, 2014
“With Design Compiler Graphical's advanced congestion and MCMM optimizations, we are seeing 20 percent less congestion in high-density cell areas, improved design frequency, lower leakage power and faster place-and-route run times.”
Mogens Isager, lead developer, Physical IC Design at Oticon, Inc.             

Sep 22, 2014
“Design Compiler's new monotonic area optimization reduced design area by 10 percent for multiple designs while meeting timing requirements and lowering leakage power.”
Michihiro Okada, general manager of the Software 3 R&D Division, Corporate Software Development Division at KYOCERA Document Solutions Inc.

“We are seeing up to 10 percent reduction in gate count simply by using the latest release of Design Compiler.”
Armin Kemna, director Design Support at Elmos Semiconductor

Jun 03, 2014
“By building on our successful collaboration on Intel's 22-nm design platform, we have been able to seamlessly extend the solution to our 14-nm process technology.”
Ali Farhang, vice president, Design and Enablement Services, Intel Custom Foundry

May 01, 2014
“With Design Compiler Graphical, we are experiencing 10 percent faster timing and very tight correlation to IC Compiler, which enables us to identify and fix design issues early in the flow.”
Tzvika Shmueli, senior director, backend chip design at Mellanox Technologies

Jan 29, 2014
“With Design Compiler Graphical we were able to achieve 5 percent higher frequency and 7 percent smaller area.”
Menachem Stern, vice president of research and development at CEVA

Jan 28, 2014
“Adding Design Compiler's early design exploration and innovative physically aware synthesis to our Customized SoC flow accelerates collaboration between logical and physical design. We can achieve a 33 percent design density improvement with this new flow.”
Akihiro Yoshitake, general manager of Technology Development Center at Fujitsu Semiconductor

Sep 03, 2013
“Reducing area and power consumption while meeting performance goals is critical to the success of mobile SoCs targeted for today's mobile computing devices. "We are using Design Compiler Graphical to help us deal with such technical challenges, and through the tight correlation with IC Compiler we achieve predictable implementation that meets our target design schedules to deliver value-added products for our customers.”
Kee Sup Kim, vice president of System LSI Infrastructure Design Center, Samsung Electronics