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Improving Design Power and Performance with RTL Architect
Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code. The first difficulty occurs during elaboration and synthesis. The RTL is converted to gates and the references to the source code are lost. The second difficulty is the gate-centric, implementation, PPA reports. The reports are designed to identify place and route issues on gate-level timing paths which is not useful to identify opportunities to improve RTL. In this webinar, Synopsys will demonstrate how to use RTL Architect™ to analyze power and restructure RTL.
Attend this Synopsys webinar to learn how to:
- Analyze RTL to identify the largest contributions to power dissipation
- Perform advanced glitch analysis using the hybrid PrimePower flow
- Perform RTL restructuring tasks: group, ungroup and reparent
- Hear from a Synopsy customer about their experiences using RTL Architect
Speakers
Listed below are the industry leaders scheduled to speak.
Vivek Rajan
Senior Principal Engineer
Intel
Vivek Rajan received his bachelor's degree in Electrical Engineering from IIT Kharagpur, India and a Master’s degree in Electrical Systems Engineering from University of Connecticut. He has 20+ years of experience in Digital Design Methodology, Chip Integration, Technology, CAD, 3DIC and mode of work (MOW) co-optimization. Vivek actively advocates for adoption of big changes to work models for higher productivity methodology. He raises awareness and drives innovation about emerging shifts in chip integration and abstraction levels for early planning, co-optimization and Silicon, Package, Board Co-Design. He is an invited speaker for Industry conferences.
Roshith Krishna
SoC Design Engineer
Intel
Roshith Krishna received his Master’s degree in Electrical Engineering from Arizona State University. He has 10+ years of experience in Digital Circuit Design, Synthesis, APR flows and Layout & Timing Integration. He likes to follow new technologies and his interests lies in finding novel ways to improve flows and methodologies for faster overall design convergence. Outside of work, he enjoys travelling and photography.
Jeffrey Lee
Applications Engineer, Senior Staff
Synopsys
Jeffrey Lee is a Product Engineer part of the New Product Introduction team. He is currently working on deploying RTL Architect to a broader customer base. His experience includes working on Design Compiler® NXT and Power Compiler™.
Vinkesh Prajapati
Applications Engineer, Senior Manager
Synopsys
Vinkesh Prajapati has over 15 years of experience in product and applications engineering focussing on RTL2GDSII solutions.
He is currently managing the product engineering teams for RTL Architect and Design Planning solutions based out of Bangalore, India.
Jim Schultz
Product Marketing Manager
Synopsys
Jim Schultz is the product marketing manager for RTL Architect. He has a rich background that includes both chip design and product engineering in processor, network and security markets.
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RTL Architect
Accurately
predict the PPA impact of architectural changes without waiting for feedback from the
physical design team
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The industry’s first physically-aware RTL analysis, exploration, and optimization system with signoff technology integration.
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