Custom Compiler Assistants Webisodes Series

Welcome to the Custom Compiler Assistants webisode series. This is a collection of short technical webinars focusing on the unique features of Synopsys’ visually-assisted automation technologies that speed up custom design tasks, reduce iterations and enable reuse. In the coming months, we will add more new webisodes to this page to provide a quick overview of the differentiating features in Custom Compiler that can shorten FinFET design tasks from days to hours.

If you have suggestions for specific topics you’d like us to address, feel free to send us a message (click on Add Comments below) and we’ll do our best to accommodate them in future webisodes.

Webisode 6: Reducing Analog Cell Layout Time with the Symbolic Editor

In this webisode we tackle analog cell layout and showcase more of the symbolic editor features that enable analog layout engineers to complete their layout in minutes vs. hours. We highlight device matching, device folding and resistor chaining.

Chris Shaw, Technical Marketing Manager, Synopsys 
Hau-Yung Chen, Sr. Director, Custom Compiler R&D, Synopsys

Webisode 5: Using the Symbolic Editor for Rapid Custom Digital Cell Layout

This webisode highlights how layout engineers can rapidly generate layout for custom digital circuits using Custom Compiler’s Symbolic Editor. We show how to interactively build floorplans at an abstract level, how to build multi-row cells—a key requirement for 7nm cell development, and how to use cell templates to quickly define the row and power structure.

Chris Shaw, Technical Marketing Manager, Synopsys
Fred Sendig, Synopsys Fellow

Webisode 4: In-Design Assistants for Resistance, Capacitance, and Electromigration Checking

This webisode highlights how Custom Compiler’s In-Design Assistants for resistance, capacitance, and electromigration checking enable layout engineers to easily verify whether their layout is meeting electrical specifications with a simple click of the mouse. We show how to selectively check critical nets in the design and report on their resistance, capacitance, and EM violations directly from the layout, without the need for an LVS-clean design.

Chris Shaw, Technical Marketing Manager, Synopsys
Fred Sendig, Synopsys Fellow

Webisode 3: In-Design Assistant for DRC

This webisode highlights how Custom Compiler’s In-Design assistant for DRC enables layout engineers to easily check their layout for design rule correctness with a simple click of the mouse. We show how to selectively check portions of the design and how to set up select categories of checks and save them for future use. In addition, we show how to highlight violations and query the error types.

Chris Shaw, Technical Marketing Manager, Synopsys
JT Li, VP of Engineering, Synopsys

Webisode 2: Routing Assistant

This webisode highlights how Custom Compiler’s routing assistant enables layout engineers to route hundreds of connections with a simple click and drag of the mouse. We show how to rapidly route complex interdigitated layouts of FinFET devices, as well as simple multi-row placements for PMOS and NMOS transistors.

Chris Shaw, Technical Marketing Manager, Synopsys
Philippe McComber, Sr. Staff Engineer, Synopsys

Webisode 1: Symbolic Editor

This webisode highlights how the symbolic editor enables layout engineers to create and optimize device placements at a high level of abstraction. We show how to rapidly create complex layout patterns for FinFET devices, as well as multi-row placements for PMOS and NMOS transistors, at a symbolic level without having to worry about design rules, connectivity or parameter values.

Chris Shaw, Technical Marketing Manager, Synopsys
Fred Sendig, Synopsys Fellow