Weikai Sun: Three different pressures are squeezing design teams. There is specification pressure – the bar keeps getting higher for speed and bandwidth, and each new protocol brings new complexities. There is pressure from shrinking time to market – by the time you are done with your current chip, you are already late with the next one! And, there is pressure from new process technologies. Advanced node processes are not friendly for analog/RF. Each new process node is bringing new challenges – there are new rules, they have reduced headroom and noise floor, issues with reliability, such as self-heating and electromigration, etc.
One of the key issues designers face is coping with parasitics. I completed my Ph.D. under Wayne Dai at UC Santa Cruz and my research was on parasitic extraction. At that time, in the late 90s, interconnect delay was starting to dominate performance and becoming a focus for designers. Now consideration of layout parasitics is paramount – you can’t optimize a design from just the schematic. In a sense, the layout is now the schematic.