Test SIG Event at ITC 2016

Test SIG at ITC 2016

In the videos below, recorded out the 24th Annual Test SIG Event at ITC 2016, Test experts Toshiba, Bosch and STMicroelectronics describe how they are using the newest capabilities in Synopsys’ comprehensive test and yield solution. Topics include faster ATPG with fewer patterns, in-system self-test in automotive designs and 7nm manufacturing test readiness.

Experience and Results Using TetraMAX II

Tetsu Hasegawa

Toshiba Corp

How BIST Can Address Functional Safety Requirements in Automotive ICs

Christophe Eychenne

Robert Bosch SAS

Benefits of a Cell-aware Flow

Roberto Gonella

STMicroelectronics

Speakers:

Tetsu Hasegawa

Toshiba

Tetsu Hasegawa joined Toshiba in 1999 after receiving his MSEE degree from Chiba University, Japan.  He and has spent that last 16 years working in DFT methodology development and is currently Chief Specialist of DFT at Toshiba. Hasegawa-san’s division is responsible for the DFT methodology supporting most of Toshiba’s small-to-large designs encompassing a variety of application areas, including automotive.

Christophe Eychenne

Bosch

Christophe Eychenne is DFT architect at Bosch in France.  He has worked many years in the semiconductor industry, first as ASIC designer and later as DFT architect and team leader at NXP, ST Ericsson and STMicroelectronics. At Bosch, a major focus for Christophe is the development of test methodologies to ensure functional safety in automotive ICs.  He lives in Sophia with his wife and two children and enjoys completing in 15K and 20K trail races.

Roberto Gonella

STMicroelectronics

Roberto Gonella earned degrees in Electronic Engineering from Politecnico of Turin (I) and Institut National Polytechnique of Grenoble (F). He joined STMicroelectronics, Crolles, France in 1996, where he worked on advanced interconnect reliability and latch-up characterization in the R&D Reliability Department. Since 2001 Roberto has been part of the R&D Process Development team, where he was first in charge of interconnect development, then, starting in 2006, continuously responsible for yield ramp-up of advanced CMOS nodes and their derivative technologies. Since his appointment as Director of Technology Development in 2015, Roberto has extended his responsibility to the technology modelling team.  The main domains of his expertise are in the fields of yield and statistical analysis, fault segregation, test and diagnostics, semiconductor physics, and technology development.