SNUG Silicon Valley 2016: Design Compiler Lunch and Learn

Accelerating Innovation with Design Compiler

Moore's Law continues to advance, providing designers with more available transistors, increased performance, and lower power than ever before. In addition, the enhancement of mature semiconductor technologies enables better silicon utilization, performance, and power for a broad range of applications, including automotive, wearable technology, and healthcare devices. 

One thing designers using these technologies share is the drive to accelerate innovation - the lifeblood of a modern semiconductor design company. This video features a panel of Design Compiler users from MediaTek, Cavium and GUC who share how they are using Design Compiler Graphical to address their IC implementation challenges for faster performance, lower power, reduced congestion and faster design convergence.

Panelists:

Eyal Odiz

VP of R&D, Design Group
Synopsys

Eyal Odiz is Vice President of Engineering at Synopsys, where he is responsible for RTL synthesis, test automation and low power. He manages a large international R&D team and works closely with key customers in the semiconductor, system, and ASIC arenas. Prior to joining the company in 2002, Eyal held executive-level positions at Synplicity and Exemplar Logic. He holds an MS in Computer Science and a BS in Civil Engineering from Technion-Machon Technologi Le’ Israel. 

Meena Gupta

Principal Engineer 
Cavium

Meena Gupta is a Principal Engineer at Cavium in San Jose, where she is a physical design engineer working on high-performance networking chips using 28nm technologies. Meena has over 15 years’ experience in IC design at semiconductor and EDA companies with expertise in both front end and back end design implementation. 

Chino Lin

Deputy Technical Director of Design Methodology 
MediaTek 

Chino Lin is Deputy Technical Director of Design Technology at MediaTek in San Jose, where his responsibilities include IP hardening, low power methodology, and advanced node flow development. Chino has more than 27 years’ experience in IC design at semiconductor and EDA companies with expertise in both front end and back end design implementation. 

Kazuyuki Irie

Department Manager of Design Services Group
Global Unichip Corporation

Kazuyuki Irie is Department Manager of the Design Service group at Global Unichip Japan. He leads the team that is developing an advanced design flow and comprehensive implementation methodology for their ASIC business. Kazuyuki has more than 20 years’ experience in ASIC design and management at Japanese semiconductor companies with expertise in both front end and back end design implementation.