SNUG Silicon Valley 2015: Design Compiler Lunch & Learn

Accelerating Innovation with Design Compiler

Watch and learn how your peers are leveraging the latest Design Compiler technologies to deliver amazing innovations in their IC products. NVIDIA presents on synthesizing high-performance cores using Design Compiler Graphical. And ARM describes ways to accelerate implementation of the energy-efficient ARM Cortex-A72 processor.

Panelists:

Eyal Odiz

VP of R&D, Design Group
Synopsys

Eyal Odiz is Vice President of Engineering at Synopsys, where he is responsible for RTL synthesis, test automation and low power. He manages a large international R&D team and works closely with key customers in the semiconductor, system, and ASIC arenas. Prior to joining the company in 2002, Eyal held executive-level positions at Synplicity and Exemplar Logic. He holds an MS in Computer Science and a BS in Civil Engineering from Technion-Machon Technologi Le' Israel.

Purnabha Majumder

Sr. Manager, Hardware Engineering 
NVIDIA

Purnabha is responsible for design and implementation including synthesis and timing closure of Tegra SoC ICs with specific focus on CPU design. Before joining NVIDIA 8 years ago, Purnabha has held IC design and R&D engineering positions in Semiconductor and EDA industries respectively. One of Purnabha's many interests lies in the area of architecture, design, and implementation of high-frequency and low-power CPUs. Purnabha has authored multiple technical publications. He holds a BS degree in Electrical Engineering and Computer Science. 

Haroon Gauhar

Principal Design Engineer 
ARM

Haroon is a member of the physical design team that worked on the Cortex-A57 and Cortex-A72 application processors. Previously, he worked in the CAD team for the Cortex-A8 and Cortex-A15 processors. Before joining ARM, Haroon worked at Calxeda, NVIDIA, Synopsys and Integrated Device Technology. Haroon is a proud Ohio State Buckeye, the current NCAAF national champions!