SNUG Silicon Valley 2014: Design Compiler Lunch and Learn
View this video of the 2014 Design Compiler Lunch and Learn and hear users discuss their experiences using new Synopsys synthesis technologies to meet the challenges of complex designs at both established and advanced nodes. You will learn how Design Compiler Graphical helps achieve smaller area, reduced congestion and faster convergence. Additionally, find out how the latest capabilities in DC Explorer help accelerate the development of high-quality RTL.
VP of R&D, Design Group
Director of SoC Design Methodology