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SNUG 2017 Custom Compiler Lunch Videolog
Cutting FinFET Layout Tasks from Days to Hours
The 2017 SNUG Silicon Valley Lunch & Learn presentations focused on how customers are using Custom Compiler to improve design productivity for FinFET.
The pioneering visually-assisted automation of Custom Compiler can cut layout tasks from days to hours. FinFET devices have added significant complexity to the design flow, and many companies are seeking new solutions for custom design.
On March 23, 2017, Synopsys hosted a Custom Compiler Lunch & Learn at SNUG in Santa Clara, CA. At this event, several industry leaders presented their experiences meeting the challenges of FinFET custom design, and discussed how they have deployed Synopsys Custom Compiler to improve their custom design productivity for FinFET.
Event Emcee
Dave Reed
Director of Marketing, Synopsys
Improving Memory Compiler Development Efficiency using Custom Compiler
Sachin Gulyani
Sr. Manager, Embedded Memories Group, STMicroelectronics
Layout Productivity Boost with Custom Compiler
Jay Yu
Director, Analog Design & Circuit Technology, MediaTek
Adoption of Custom Compiler Co-Design with IC Compiler II for In-Vehicle Designs
Shinichiro Oshige
Sr. Manager, Renesas Electronics
IP Development using Custom Compiler: Accelerating FinFET Layout
Bob Lefferts
Group Director, Mixed-signal IP, Synopsys