The 2017 SNUG Silicon Valley Lunch & Learn presentations focused on how customers are using Custom Compiler to improve design productivity for FinFET.
The pioneering visually-assisted automation of Custom Compiler can cut layout tasks from days to hours. FinFET devices have added significant complexity to the design flow, and many companies are seeking new solutions for custom design.
On March 23, 2017, Synopsys hosted a Custom Compiler Lunch & Learn at SNUG in Santa Clara, CA. At this event, several industry leaders presented their experiences meeting the challenges of FinFET custom design, and discussed how they have deployed Synopsys Custom Compiler to improve their custom design productivity for FinFET.
Dave Reed
Director of Marketing, Synopsys
Sachin Gulyani
Sr. Manager, Embedded Memories Group, STMicroelectronics
Jay Yu
Director, Analog Design & Circuit Technology, MediaTek
Shinichiro Oshige
Sr. Manager, Renesas Electronics
Bob Lefferts
Group Director, Mixed-signal IP, Synopsys