PrimeTime Special Interest Group (SIG) at DAC 2015

The Synopsys PrimeTime SIG is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA). 

Maximize Design Productivity with Advanced Signoff Technologies

A PrimeTime SIG event, Maximize Design Productivity with Advanced Signoff Technologies, was held in San Francisco, California, during DAC on June 8, 2015. PrimeTime users and managers from top semiconductor companies attended the event.


Presenters from Broadcom, GLOBALFOUNDRIES, and STMicroelectronics shared their timing signoff and closure experiences with advanced signoff technologies of PrimeTime, StarRC, and SiliconSmart. Members of the PrimeTime, StarRC, and SiliconSmart R&D teams were also present during this event.


Robert Hoogenstryd


Robert, Senior Director of Marketing for Design Analysis and Signoff tools, kicked off the event and welcomed the audience. Robert described the top challenges designers face in the signoff flow at established nodes as well as advanced nodes. 

Jacob Avidan


Jacob, Vice President of Engineering for the PrimeTime team, presented an overview of the latest Internet of Things innovation in timing, including a review of recent customer successes with advanced signoff technologies, an exciting announcement of upcoming features, and his vision of the future of signoff timing technologies. 

Louis Chui


Louis, Technical Director, stated that affordable scalability is a key signoff challenge for Broadcom. Despite PrimeTime’s recent 30% memory reduction, their biggest chips still require 320-512GB systems per scenario. By bringing in HyperScale, Broadcom was able to demonstrate a 8X reduction in memory and 7X speedup on a 100M+ instance design.

Ramya Srinivasan


Ramya, Member of Technical Staff, shared that very low voltage versions of planner and FinFET processes are driving the need to reduce margin and pessimism. She sees key helpful technologies such as PrimeTime's Parametric On-Chip-Variation (POCV) and Advanced Waveform Propagation (AWP), even for ultra-low power 28-nm process, as the answer to address these issues.

Sebastien Marchal


Sebastien, Principal Engineer, highlighted StarRC's simultaneous multi-corner (SMC) extraction ability to cut runtime by 2-3X and disk space by 2X using the same number of cores more efficiently. He also shared how PrimeTime's noise ECO fixing was able to address noise violations in top channels that previously could not be fixed by wire spreading, and why PrimeTime's unique capability of fixing noise violations at coupling source is critical to achieve the best quality of results.