DAC 2016 Custom Compiler Luncheon Videolog

Cutting Layout Tasks from Days to Hours

FinFET devices have added significant complexity to the design flow, and many companies are seeking new solutions for custom design. Custom Compiler’s pioneering visually-assisted automation can cut layout tasks from days to hours. On June 7, 2016, Synopsys hosted a Custom Compiler Luncheon at DAC. At this event, attendees heard users from GSI, Samsung, STMicroelectronics and Synopsys’ IP Group discuss their experiences with custom design challenges and how they have deployed Custom Compiler to improve their custom design productivity for FinFET and established nodes.

Guest Speakers:

Antun Domic

Exec. VP and GM, Design Group, Synopsys

Event Emcee 

Antun Domic serves as executive vice president and general manager of the Design Group at Synopsys, Inc., where he is responsible for leading the development of the company’s implementation and analog/mixed-signal product lines. Prior to joining Synopsys in 1997, he worked at Cadence Design Systems; at the Microprocessor Group of Digital Equipment Corp., and at the Massachusetts Institute of Technology (MIT) Lincoln Laboratories. Antun earned a BS degree from the University of Chile in Santiago, and a PhD in Mathematics from MIT. 

Randy You

CAD Manager, GSI Technology

Adopting Custom Compiler to Improve Layout Productivity for Advanced Nodes 

Randy is a CAD manager at GSI. He has a strong background in custom CAD tools, including front-end, back-end and simulation tools. Prior to GSI, he worked at Valid Logic, Zilog and Hynix doing custom CAD flow development and support and maintenance of CAD tools. Randy received his B.S. degree from Tatung University, Taipei, Taiwan and an M.S. in Electrical Engineering from Southern Methodist University, Dallas, Texas.

Bonhyuck Koo

Principle Engineer, Samsung

Custom Design Using iPDK with Custom Compiler at Advanced Nodes

Bonhyuck Koo is a principle engineer in the design services team at Samsung. He is in charge of PDK library development, including iPDK, PCell and custom layout automation. He has spent many years in the custom IC design field and has experience developing PDKs, physical verification rule decks, custom layout automation flows and design methodologies. He earned his BS and MS in semiconductor thin film materials from the University of Yonsei in Seoul.

Atul Bhargava

Sr. Staff Engineer, STMicroelectronics

Custom Compiler Adoption at STMicrolectronics for Design Development Efficiency 

Atul Bhargava is a Senior Staff Engineer at STMicroelectronics. He started his career with the ST Foundry team, where he worked on various technologies and tools ranging from 1-micron to 14nm, addressing back-end methodologies to simulator usage. He has been actively working on performance improvement in layout tools, 3D extraction, and a variety of reliability topics like EM/IR and other aging effects. He was instrumental in initiating Laker usage in ST India several years ago. Key methodologies that have emerged from his work include Simultaneous Multi-Corner extraction, which is being presented at DAC this year, and Block-level Electromigration, which was presented at DAC 2 years ago.

Phil Morris

Engineer, IP Group, Synopsys

Addressing FinFET IP Layout Challenges with Custom Complier 

Phil Morris is an engineer in Synopsys’ mixed-signal IP group. He joined Synopsys in 2014 as part of the DDR acquisition after spending several years as a mixed-signal circuit design engineer for AMD. Prior to that, he worked as a layout engineer with Analog Integration in the UK. Phil completed his Master’s degree in Science at the University of Westminster.