Join Us for a Workshop

Ethernet PHY Design Methodology and Hands-On Custom Compiler Experience

Friday, December 7, 2018, 10:45 a.m. – 2:30 p.m.

Synopsys, Inc.
690 E. Middlefield Road,  Building A, Mountain View, CA 94043

Seating is limited. Registration required.

Ethernet PHY and Custom Compiler Workshop

Designers are constantly working towards higher performance designs to meet the insatiable need for more network bandwidth. New process technologies enable designers to deliver more performance, but at the cost of significantly more design effort. Challenges introduced by the latest process technologies include the divergence between pre-layout and post-layout simulations, high interconnect parasitics, and the need to design for reliability. 

At this workshop, you will hear from the Synopsys DesignWare® IP team about our high-speed 56G Ethernet PHY IP design project’s key findings, illustrating how designers can optimize their design methodology to overcome challenges, while meeting aggressive schedules. Attendees will go through a hands-on experience using Custom Compiler’s productive layout features, which helped the Synopsys IP team optimize their design methodology for successful design and delivery of 56G Ethernet PHY.

In this workshop, you will:

  • Learn about the need for high-speed PHY technology for 400G and beyond Ethernet applications and what design considerations and methodology flows are required for such high-speed Ethernet SoCs
  • Use the Custom Compiler design environment to build a voltage regulator amplifier layout in 3X less time and minimize circuit/layout design iteration by extracting early parasitics, and checking and fixing electromigration issues sooner

 

Ayal Shoval

Ayal Shoval

Senior Member, Technical Staff, IP, Solutions Group, Synopsys

Maged Attia

Maged Attia

Product Marketing Director, Custom Design Product Group, Synopsys

Agenda

10:45 - 11:00 a.m.

Welcome/Registration/Networking

11:00 - 12:00 p.m.

Latest Innovations in 56G Ethernet PHY Presentation

12:00 - 1:00 p.m

Lunch and Custom Compiler Overview Presentation

1:00 - 2:30 p.m.

Hands-On Experience with Custom Compiler: Visually-Assisted Automation for Analog Layout