Designers are constantly working towards higher performance designs to meet the insatiable need for more network bandwidth. New process technologies enable designers to deliver more performance, but at the cost of significantly more design effort. Challenges introduced by the latest process technologies include the divergence between pre-layout and post-layout simulations, high interconnect parasitics, and the need to design for reliability.
At this workshop, you will hear from the Synopsys DesignWare® IP team about our high-speed 56G Ethernet PHY IP design project’s key findings, illustrating how designers can optimize their design methodology to overcome challenges, while meeting aggressive schedules. Attendees will go through a hands-on experience using Custom Compiler’s productive layout features, which helped the Synopsys IP team optimize their design methodology for successful design and delivery of 56G Ethernet PHY.
In this workshop, you will: