DAC 2018 Custom/AMS Luncheon Videolog


Accelerate Circuit Verification in 3D Flash Memory using FineSim

Yusuke Ono

CAD Engineer, Toshiba Memory Corp.

Yusuke Ono is a CAD Engineer at Toshiba Memory Corporation with more than 14 years’ experience. For the past 6 years, he has been involved in Flash memory design methodology, with a focus on circuit simulation and its environment.

He received a B.S. in Electrical Engineering from Tokyo Metropolitan University.

Full-Chip Self-Heat Prediction using Machine Learning

Miloni Mehta

Sr. Hardware Engineer, NVIDIA

Miloni Mehta is a Sr. Hardware Engineer in the VLSI global circuits team at NVIDIA. Her work mainly focuses on clock design for NVIDIA’s GPU/SoC chips. She is excited to be here at DAC to highlight one of the many applications of Machine Learning that the VLSI community can benefit from.

Before joining NVIDIA, she earned her MSEE from the University of Michigan. In her free time, Miloni enjoys hiking and travelling.

Rapid Development of Mixed-Signal IP with Custom Compiler

Varun Ramaswamy

Mixed-Signal Design Manager, Seagate

Varun Ramaswamy is a founding member of the Mixed-Signal VLSI development team at Seagate and heads design methodology, physical verification and foundry relations for the mixed-signal team. During the past 10 years he has been involved in the development of various mixed-signal IP, such as high-speed PLLs, HDD read channels, DDR PHYs, SRAMs, and temperature sensors, amongst others.

He holds a Master’s degree in Electrical Engineering from the University at Buffalo (SUNY). His current research interests are in the application of Machine Learning for reliability analysis in analog/mixed-signal circuits.

First-Pass MRAM Design Success in Three Months using Custom Compiler Environment

Charles Farmer

Design Engineer, Numem

Charles Farmer is a design engineer with Numem (NVM Engines). He has designed both full-custom and compiler-based SRAM and cache memory devices at Broadcom, MediaTek, Analog Devices, and AMD.

Charles has a BSEE degree from Mississippi State University, and has worked in the industry for 30+ years.

Automating Physical Design of an Energy-Efficient Machine-Learning Processor using Custom Compiler Environment

Michael Dierickx

Physical Design Manager, Esperanto Technologies

Michael Dierickx is the Physical Design Manager at Esperanto Technologies, an exciting machine-learning start-up. Previously, he designed SRAMs and global circuits and owned full-chip place-and-route at Intel, Sun-Oracle, and MoSys.

Michael earned his MSEE from Stanford University and began his career designing custom data paths for the Cell Microprocessor with IBM.