Designers are constantly working towards higher performance designs to meet the insatiable need for more network bandwidth. New process technologies enable designers to deliver more performance, but at the cost of significantly more design effort. Challenges introduced by the latest process technologies include the divergence between pre-layout and post-layout simulations, increased number of design rules, and the need to design for reliability.
At this workshop, attendees will get hands-on experience using Custom Compiler’s productive layout features, which were developed with input from industry technology leaders and Synopsys' own IP development group, leveraging experiences from different technologies from regular planar nodes to the most recent FinFET technologies.
In this workshop, you will:
- Use the Custom Compiler design environment to build the layout of a PLL output clock driver
- Leverage advanced features such as placement assistants for device and cell level placement exploration, and routing assistants for quick routing
- Verify the layout using DRC, LVS and extraction interfaces.