Silicon Valley Arm-Synopsys Workshop 2018

May 24, 2018

Synopsys, Inc.
445 N. Mary, Building 2, Sunnyvale, CA 94085

Join us to hear a keynote presentation from Arm and in-depth technical presentations from Arm and Synopsys experts, ecosystem partners and users. Topics include:

  • Accelerate software bring-up and system validation leveraging Arm® Fast Models, Cycle Models and debugger in Synopsys® tools
  • Optimize Arm-based SoC implementation using Synopsys Design Platform with Fusion Technology™
  • Achieve optimal Power, Performance, and Area (PPA) on latest Arm Cortex®-A processors and Arm DynamIQ™ technology
  • Accelerate power integrity closure with RedHawk™ Analysis Fusion within IC Compiler™ II
  • Maximize verification ROI with Synopsys Verification Continuum™

Watch John Heinlein, Vice President and Chief of Staff to the CEO, Arm deliver the keynote for the Arm-Synopsys Workshop in the Silicon Valley.

Accelerating Arm-based SoC Design and Verification

Agenda

9:00      Check-in and Refreshments

10:00    Opening Remarks

10:05    Keynote Address: Architecting a Connected Future

10:50    Break

Presentation Abstracts

Keynote Address

10:05 AM – 10:50 AM
Architecting a Connected Future
John Heinlein, Vice President, Chief of Staff to the CEO, Arm


As the march towards one trillion connected devices continues, companies are building products that touch every aspect of modern life, from the cars we drive to the to the streetlights which line the streets in a connected city. These products are starting to use technologies like virtual and augmented reality, machine learning, and hardware- and software-based security.

Arm has expanded its focus beyond mobile into these new areas and is working with the design ecosystem to enable this next generation of secure, connected devices. These technology advances raise the complexity of the overall system and create a demand for increasingly sophisticated approaches for design and verification. Arm works with partners like Synopsys to address these challenges and minimize the risk of designing with the latest processor cores.

Design Track

11:00 AM – 11:30 AM
Synopsys Design Platform with Fusion Technology for Arm®-based designs
Michael Jackson, Corporate Vice President, Marketing and Business Development, Design Group, Synopsys

Learn about the latest developments on the Synopsys Design Platform to improve PPA for Arm®-based designs. Understand how the breakthrough Fusion Technology transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff tools, enabling you to accelerate the delivery of your next-generation designs with the industry-best full-flow QoR and the fastest time-to-results. Customer examples and QuickStart Implementation Kits (QIKs) are also shared.

11:30 AM – 12:15 PM
High-Performance Arm®-based CPU Implementation for Mobile Devices
Using Synopsys Design Platform with Fusion Technology
Brian Millar, Senior Principal Engineer, Microprocessor Implementation Specialist, Samsung Austin R&D Center

Listen to customer experiences and learn about their methodologies for achieving design goal metrics. Find out more about the end-market applications in automotive, mobile, server, networking, and IoT.

 

1:15 PM - 2:15 PM
Best Practices and QIKs for the Latest Armv8-A Processors
Michael Montana, Principle Applications Engineer, Design Group, Synopsys
Rupal Gandhi, Technical Marketing Lead, Physical Design Group, Arm

Learn from Synopsys tool experts the best practices and technologies to efficiently implement Arm's next-generation Armv8-A processors at 12/7nm to meet challenging performance targets, while minimizing dynamic and leakage power. Technology highlights include optimized implementation of compute-intensive modules to push performance while limiting IR drop, efficient leakage power optimization using multiple VT/channel width libraries, and optimized clock gating implementation.

2:15 PM - 3:00 PM
ANSYS: RedHawk Analysis Fusion Signoff-driven Flow within IC Compiler II
Annapoorna Krishnaswamy, Product Marketing Manager, ANSYS

Understand how to achieve early, accelerated design optimization for power integrity and reliability with the RedHawk Analysis Fusion signoff-driven flow within IC Compiler II. Experience how the seamless integration enhances ease-of-use with virtually no learning curve, and enables up to 5X turnaround time improvement vs. point tool power integrity fixing flows.

3:15 PM - 4:00 PM
Latest Implementation Technology Update - Part 1
Daniel Biset, Principal Applications Engineer, Design Group, Synopsys

Learn about the challenges posed for high-performance, energy efficient implementation, and how IC Compiler II can help optimize PPA and accelerate time-to-market with its convergent flow that concurrently addresses congestion, timing, power, and area goals. Find more about advanced node requirements, and IC Compiler II's color-aware, multi patterning place-and-route flow. Finally, hear about the benefits of utilizing the in-design capabilities of IC Validator.

 

4:00 PM - 4:45 PM
Latest Implementation Technology Update - Part 2
Daniel Biset, Principal Applications Engineer, Design Group, Synopsys

Learn about advanced node synthesis challenges, and how Design Compiler Graphical can help achieve best-in-class quality-of-results with support for via ladders, layer aware optimization, pattern-must-join, inbound cell and pin access optimization. Realize high-performance, energy-efficient signoff closure with PrimeTime (PBA-based ECO and power recovery, exhaustive PBA runtime gains), StarRC (simultaneous multi-corner and incremental extraction), and Custom Compiler co-design.

Verification Track

11:00 AM – 11:30 AM
Synopsys Verification Continuum Solution for Arm-based Designs
Tom De Schutter, Director of Marketing for Prototyping, Verification Group, Synopsys

Arm and Synopsys are partnering to address the verification challenges of today's complex electronics designs. This session will provide an overview of the Synopsys Verification Continuum platform and explain how it addresses power optimization, software bring-up, functional verification and system validation. Attendees will get a better view of Synopsys’ overall verification solution. Subsequent sessions in this workshop will provide more details about the value of the Verification Continuum for various verification use cases.

11:30 AM – 12:15 PM
Low Power Verification and Analysis - From Architecture to Signoff
Tony Dimalanta, Senior Staff Applications Engineer, Verification Group, Synopsys

Low power is a key differentiator for Arm-based SoC designs – from wearable devices to mobile and server applications. SoC design teams deploy multiple low power techniques to achieve aggressive low power targets. This session will cover how Synopsys Low Power flow is used to manage SoC power consumption from architecture to RTL to gate level power signoff. The UPF-based low power verification flow using static and dynamic engines will also be covered. Case studies will highlight how SoC design teams have successfully used these flows to achieve their low power targets.

1:15 PM - 3:00 PM
Accelerate Software Bring-up and System Validation to Pull-in Time-to-Market
Malte Doerper, Staff Product Marketing Manager for Virtual Prototyping, Synopsys

Bill Neifert, Senior Director of Market Development, Development Solutions, Arm

The differentiation of today’s electronic devices is more and more driven by software and connectivity. Due to the increased system complexity the challenges of product failures and time-to-market delays are growing dramatically. This session is dedicated to explaining how the Synopsys Verification Continuum platform helps to address these challenges by accelerating software development and system validation using virtual prototyping, emulation and FPGA-based prototyping. Arm and Synopsys will talk about their latest technologies and demonstrate how the close integration between Arm's Fast Models, Cycle Models and DS-5 software debugger with Synopsys virtual prototyping and hybrid solutions is shifting left the complete development cycle.

3:15 PM - 4:45 PM
Maximize SoC Verification ROI and Reduce Time to Closure
John Sotiropoulos, Staff Applications Engineer, Verification Group, Synopsys
Jonah Deitz, Staff Applications Engineer, Verification Group, Synopsys

According to Synopsys’ 2017 Global User Survey, the number one reason for tapeout delays is functional verification taking longer than planned. Bug escapes at each stage of verification are much costlier to fix downstream, especially for Arm-based SoC designs where time-to-market is of extreme importance. This session will provide a broad overview of Synopsys’ functional verification solutions for simulation, planning, coverage, execution management, Verification IP, static, formal and advanced debug. The native integration of these verification engines provides an additional boost in performance and productivity resulting in faster convergence and time to verification closure.

* Some presentation material and videos are available to Synopsys customers only