Israel Arm Synopsys Workshop 2018

Nov. 06, 2018

Dan Accadia Hotel
Ramat Yam St 122
Herzliya, Israel

Join us to hear a keynote presentation from Arm and in-depth technical presentations from Arm and Synopsys experts, ecosystem partners, and users. Topics include:

  • Optimize Arm-based SoC implementation using Synopsys Design Platform with Fusion Technology™
  • Achieve optimal power, performance, and area (PPA) on latest Arm Cortex®-A processors and Arm DynamIQ™ technology
  • Accelerate power integrity closure with RedHawk™ Analysis Fusion within IC Compiler™ II
  • Synopsys Verification Continuum® Solution for Arm-based Designs
  • Low Power Verification and Analysis from Architecture to Signoff
  • Accelerate software bring-up and system validation leveraging Arm Fast Models, Cycle Models and debugger in Synopsys tools 
  • Maximize verification ROI with Synopsys Verification Continuum

Accelerating Arm-based SoC Design and Verification

Agenda

08:30    Check-in and Refreshments

09:15    Opening Remarks

09:20    Synopsys Keynote Address by Chi-Foon Chan, Co-CEO: Alliances and Innovation: Requirements for a Bright Future

10:00    Arm Keynote Address by Steve Roddy, Vice President, Machine Learning Group: AI at the Edge

10:35    Arm DynamIQ Technology: Redefining Multi-core Processing for the Next Era of Computing

11:05    Break

Design Track

11:15    Synopsys Design Platform with Fusion Technology for Arm-based Designs

11:45    Inomize: Arm-based SoC Implementation with Synopsys Tools

12:30    Lunch

13:15      Best Practices for High-performance, Energy-efficient Implementations of the Latest Arm Processors at 7nm

14:15      ANSYS: Accelerate Power Integrity Closure with RedHawk Analysis Fusion within IC Compiler II

15:00     Break

15:15     Latest IC Compiler II Technology Update to Optimize PPA/TTR for High-performance, Energy-efficient Implementation

15:55     Latest Design Compiler, PrimeTime, StarRC, PrimePower, and Custom Technology Update to Optimize PPA/TTR for High-performance, Energy-efficient Design Closure

16:45    Closing Remarks and Raffle

Verification Track

11:15    Synopsys Verification Continuum Solution for Arm-based Designs 

11:45    Low-power Verification and Analysis from Architecture to Signoff

12:30    Lunch

13:15      Accelerate Software Bring-up and System Validation to Pull In Time-to-Market

15:00     Break

15:15     Maximize SoC Verification ROI and Reduce Time-to-Closure

16:45     Closing Remarks and Raffle