1:1 with Li Ding

Li Ding

Changing the Pre-silicon Design Yield Analysis Game

We sat down with Li Ding, Synopsys Scientist in the Design Group, to learn more about Synopsys’ new PrimeYield statistical yield analysis solution and what impact it will have on SoC design.

Q: Synopsys recently unveiled its new PrimeYield product. What is the significance of this product?

Li Ding:

Synopsys has been the leader in design analysis and signoff for many years, with PrimeTime static timing analysis recognized as the industry’s golden signoff solution. With rising manufacturing costs at advanced nodes, designers are introducing ever-increasing design margins to manage risk and ensure yield. These margins are limiting semiconductor innovation, and are a significant challenge in designing the fastest, most efficient SoCs. PrimeYield, with its new statistical-based analysis engine, can provide guidance on ROI (return-on-investment) and optimization that improves design yield while achieving the best power, performance, and area of the designs.

Q: What makes PrimeYield different from earlier statistical yield analysis solutions?

Li Ding:

Speed and capacity, with the same golden accuracy, is the key differentiation versus other statistical analysis solutions. Statistical yield analysis is a concept that has existed for decades but was never feasible for deployment beyond a small design block—even less so in a large-scale SoC production flow. With machine learning technology, PrimeYield can complete the same statistical analysis in minutes on a single execution host that previously could take days, and with the same accuracy.

Q: You emphasized PrimeYield is applicable to the industry’s largest SoCs, why is that important?

Li Ding:

PrimeYield leverages the golden signoff PrimeTime engine that can perform SPICE-accurate timing calculations and variation modeling in seconds. However, Monte Carlo simulation for true-statistical analysis still needs to repeat the same analysis thousands, or even millions, of times for high-sigma accuracy, which is much too time-consuming to keep up with the fast pace during SoC design implementation and signoff.

PrimeYield deploys machine learning in Monte Carlo simulation, which, because of its repetitive nature, is an excellent application for machine prediction, and speeds things up by 100X to 10,000X (yes, that’s ten thousand times!), enabling full-chip SoC or high-Sigma analysis that was never feasible before.

Q: You just mentioned high-Sigma analysis. What types of designs have such high levels of yield requirements, and what were some of the challenges in doing that?

Li Ding:

High-reliability applications, like automotive designs, or small design circuits that are repeated thousands of times in an SoC, like artificial intelligence processing units, require high-Sigma yield on very targeted circuitry. High-Sigma analysis requires millions of Monte Carlo samples and can easily take weeks of computation using thousands of cores. A lot of designers choose to extrapolate existing variation models or use FastSPICE solutions, but those flows cannot provide the same level of accuracy.

PrimeYield uses the machine learning technology I mentioned before and strategically utilizes Synopsys HSPICE through native links to achieve HSPICE Monte Carlo accuracy with feasible runtimes, typically within an hour on just 4 or 8 CPU cores.

Q: What about over-designing in today’s digital design flow without true statistical guidance? What guidance can designers expect from PrimeYield?

Li Ding:

Without true statistical guidance, designers are adding design margins to every part of the design, safeguarding themselves from statistical effects. PrimeYield can identify the statistical hotspots and a sorted list of high-ROI optimization targets for design margining and/or sensitivity reduction. By addressing these strategic targets, designers can reduce statistical yield loss and improve design yield robustness without unnecessary impact to design performance and efficiency.

Q: Could you elaborate more on the concept of design yield robustness and what metrics are measured?

Li Ding:

Well, in addition to potential yield loss due to statistical effects, rare events such as unexpected process and voltage variations could also lead to yield loss. “Robustness” is the concept of design immunity from such variations. Take voltage variation, for example. Typical voltage-drop analyses are vector-driven, which simulates a known event. However, an SoC chip may encounter many different scenarios throughout its operation cycles. Evaluating robustness and improving immunity to the unknown is also a key consideration for SoC designers.

Q: How does PrimeYield fit into the Synopsys Fusion Design Platform?

Li Ding:

Today, statistical yield analysis is typically done late in the design phase, close to design signoff, due to the cost and complexity of the analysis. PrimeYield’s fast and high-capacity yield analysis engine means designers can finally optimize towards the best design PPA-Y (performance, power, area, and yield) throughout the design flow. PrimeYield is available within the Synopsys Fusion Design Platform and delivers designs with the least statistical yield loss and best design yield robustness.

Q: Thank you for sharing this in-depth look at PrimeYield with us!

Li Ding:

You're welcome. PrimeYield is an exciting new product and we look forward to helping designers minimize design time and achieve the best yield results in production.