1:1 with Michael Jackson

Michael Jackson

Synopsys Enables 98% of 10/8/7nm Designs

We sat down with Michael Jackson, Corp. VP of Marketing & Business Development, to look at advanced node design starts and tape-outs along with the latest statistics on Synopsys tool usage at 10/8/7nm.

Q: To begin with, let me ask: How do you get an accurate estimate on the number of active design starts and tape outs at advanced nodes?

Michael Jackson:

We began the process of tracking the number of active design starts and tape outs as far back as 2003 with the 90nm process node. As new nodes come online, the field team at Synopsys monitors and tracks progress of all our active customer designs. Because of PrimeTime’s pervasiveness as a signoff tool and our strong Design Compiler synthesis position, we have very good visibility into the number of designs starts and tape outs that are happening at each node.

Q: Any observations from your data on the node ramp-up over the years?

Michael Jackson:

Even with the increasing complexities that come with each new node, we have observed that typically there’s a two-year duration between the peaks of the node ramp-ups. When there are more than 450 design starts at a particular node, we stop tracking numbers at that node and focus on the next node.

Q: What are the more recent nodes that you are tracking? Any insights?

Michael Jackson:

Currently, we are tracking active design starts and tape outs at 10/8/7nm. And, I want to make a few observations and insights on Synopsys tool usage at these nodes.

Firstly, Synopsys synthesis and signoff enables 98% of the 10/8/7nm designs. Design Compiler, PrimeTime and StarRC are seeing pervasive usage at these nodes, and continue to fortify our strong position in synthesis and signoff.

Secondly, Synopsys place-and-Route enables 92% of the 10/8/7nm designs. Customers continue to increasingly deploy IC Compiler II on their 10/8/7nm designs driven by quality-of-results (QoR) and time-to-results (TTR) gains.

And finally, there are 6X more 10/8/7nm P&R tape outs exclusively with Synopsys vs. other EDA vendors.

Q: Can you further elaborate on what you mean by ‘exclusively with Synopsys’?

Michael Jackson:

If you further drill into place-and-route statistics, some designs are done solely using IC Compiler II, some designs solely use other EDA vendors’ tools, while some other design use a mixture of P&R tools.

Now, if you look at designs taped out exclusively with Synopsys P&R vs. exclusively with P&R from other EDA vendors, 6X more 10/8/7nm tape outs are done with Synopsys.

Q: Can you comment on customer adoptions at these advanced nodes?

Michael Jackson:

At 7/8nm, we have 25+ new customer adoptions, 50+ designs in development, and thousands of partitions that have already been taped out. Frankly, the Synopsys Design Platform with Fusion Technology is the leading platform for market-maker SoCs at 8/7nm.

Here are a few recent customer examples across different vertical segments:

  • We taped out the world’s largest 7nm CPU design with 1 billion+ instances last year. It was implemented 100% with IC Compiler II
  • We achieved ~80% utilization on a next-generation mobile processor. Believe me, achieving such high utilization at an early 7nm ramp-up is not easy!
  • One customer attained 2GHz+ performance on their revolutionary home network and storage design
  • We demonstrated 3% better area than our competition on a next-generation machine-learning processor. This was a significant win for our breakthrough Fusion Technology
  • In another 7nm machine-learning/data-analytics platform design, we were able to achieve 5% better area using Design Fusion that enables logic restructuring during the place-and-route. This was both a technical and business win for us.

Thank you Michael. This was very insightful. Any closing remarks?

Michael Jackson:

Well, in summary, I’d like to emphasize that Synopsys is the leading solution of choice for our customers at advanced 10/8/7nm, as observed from real data on design starts and tape outs. And, we continue to build on our leadership with active foundry and customer collaborations at the new 5/3nm design nodes and below.