Q: Synopsys recently announced a new IC Validator NXT solution for physical signoff at advanced nodes. Can you tell us more about it?
When designers start working on advanced-node designs at 7nm, 5nm, and below, they realize that physical verification complexity drastically increases, but their design timeline doesn’t. So, we looked at different ways to address the complexity problem and also reduce the overall physical verification cycle to reach final signoff.
The new technologies and features within IC Validator NXT deliver unparalleled productivity gains and enables designers to cut their physical signoff time by 2X.