Q: Samsung and Synopsys recently announced the tapeout of the industry’s first Gate-All-Around (GAA) transistor SoC. Can you tell us more about it?
Certainly. This milestone builds on our numerous successful collaborations with Samsung, and validates the readiness of GAA architecture, the next-generation transistor technology. A key benefit of GAA is the realization of enhanced gate control and reduced internal parasitics that together demand optimization technologies to extract the process’ combined power, performance, and area (PPA) potential.
My team has worked closely with Jacob’s team for several years to tightly couple PrimeTime timing and StarRC parasitic analysis with IC Compiler II to provide full-flow, total-power-driven optimization with signoff-correlated results, thus accelerating the path to targeted PPA for advanced designs. In this instance, enhancements in IC Compiler II that tightly couple technologies across the placement, legalization, and routing stages have been key to Samsung Foundry achieving its overall logic-area shrink goals for their new GAA process.