Designer's Digest

Issue #12: Formality Equivalence Checking

Welcome to the Designer's Digest!

The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power, and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Using Formality, designers are able to achieve the highest verifiable QoR with Design Compiler or Fusion Compiler. Formality guides you through the implementation of the functional ECO with minimal impact to the design and verified correctness in minutes.