Parasitic Extraction Requirements Driven by Custom Design

Ash Patel, Director of Product Marketing

Fast growing markets like 5G, biotechnology, AI, and automotive are driving the new wave in semiconductor design and the need for highly integrated system on chip (SoCs).  Power management, sensors, RF and precision analog functionality are all integrated on the same substrate which poses new challenges for custom design tools. Specifically, there are new challenges for parasitic extraction that customer design engineers need to overcome to drive SoC closure.

Inductance Extraction

Historically, capacitance was the primary component extracted since designs were most sensitive to capacitance. Then came resistance extraction and now self and mutual inductance are being extracted. Power, RF, Serdes, high speed I/O and 3D-IC are driving the necessity for inductance extraction since the frequency band of operation is pushed higher in the GHz region.

Substrate Extraction

Integrating power switching blocks with RF blocks on the same die brings substrate coupling issues to the forefront. To account for substrate during design, good extraction techniques must be implemented to augment your circuit netlist with a substrate netlist. Noise coupling analysis should be done at the substrate level so that the designer can make appropriate trade-offs before running top level simulations. 

Higher Accuracy

As the applications demand higher precision, speed or sensitivity from chips it drives the accuracy requirements for parasitic extraction higher. Traditional rule-based methods have managed to improve accuracy by improving modeling through advanced interconnect technology files, but even better accuracy can be achieved by the usage of 3D field solvers. This is even becoming an option for full-chip design.


Extraction engines must handle large layout datasets with growing chip size and increasing number of components being extracted. This requires the extraction tool to manipulate multiple gigabytes of data and scale to a multitude of cores for achieving reasonable runtime. 

Post Layout Analysis

Once the layout has been extracted over several process corners, post-layout analysis is dictated to improve TAT by reducing simulation iterations. This drives the need for command line or GUI based tools to enable post layout analysis. Some of the debug features designers will need to aid post layout analysis include what-if-analysis, RC scaling, the ability to compare parasitics, open/short debug, and incremental extraction. 

Netlist Reduction

With increasing complexity and integration in SoCs comes an increase in transistor count.  When this is coupled with the  additional parasitic components that need to be extracted for higher accuracy,  detailed netlist becomes impractical to simulate. Hence the role of netlist reducers whether standalone or part of the extraction tool or simulator have become a critical component of custom design analysis. Netlist reducers provide the capability to reduce extracted netlist sizes without compromising accuracy. They also have the flexibility to tune different portions of the circuit individually. 


Custom design and co-design needs are increasing as semiconductor end applications drive the need for higher performance and integrated functions on SoCs. These trends are driving new requirements for parasitic extraction. High speed design needs inductance extraction, and high sensitivity design needs substrate extraction and accuracy. As the number of components being extracted increase, the capacity and run-time performance of extraction engines must be enhanced, and growing netlist sizes are bringing the role of netlist reducer in to prominence to reduce the length and number of post layout simulations. With these requirements and challenges no longer hidden under the digital design umbrella, the EDA industry is focused on bringing a new era of custom design to the market.