The fact that many of these proposed shapes are curvilinear begs the question: is it time for more mainstream use of 3D extraction tools known as field solvers? The field solver, as you might recall, has the advantage of not requiring a pattern matching methodology to estimate parasitics. Rather, the field solver can take any arbitrary shape and compute R and C values by solving complex EM equations. Of course, runtime costs can be mitigated with distributed processing and tile based solutions.
The additional good news in moving to 3D field solvers is that foundry certifications become a bit simpler since the golden values for the world’s leading foundries are based on the 3D field solvers themselves.
Synopsys extraction technologies have long been the standard reference of golden parasitics, from TCAD tool flows using Raphael XT to library characterization and critical net extraction using QuickCap and finally gate level extraction of interconnect parasitics using StarRC. Together, these tools provide a complete solution from the inception of the process, to final chip delivery.
Whichever way process technologies head, it’s becoming clear that 3D field solvers will play a dominant role in both the development of process technologies and the transistor/gate level architectures that are derived from them. As foundries move towards nano-wire and gate-all-around architectures, the extraction of parasitics at 5nm and below will bring a whole new level of appreciation from those involved in the development of these technologies, especially one former STA marketeer.