IC Validator Videos

Customer Experiences

IBM + -

IBM’s Experience with IC Validator DRC Explorer to Achieve Fastest DRC Results

Juniper + -

Juniper Highlights IC Validator’s Performance Benefit: Overnight Full Chip DRC and LVS

NVIDIA + -

NVIDIA’s Experience with IC Validator for Physical Signoff of Full Reticle GPU Designs

Socionext + -

Socionext Shares Their Experience with IC Validator for Excellent Performance Scalability

DRC Videos

Learn how to setup IC Validator tool in your environment and how to change tool versions. 

Learn how to run Design Rule Checks (DRC) interactively using IC Validator VUE.

Learn how to run IC Validator incremental DRC flow by Layer/window options. 

After completion of a DRC run, IC Validator creates several output files such as  Result, Error, Summary, Tree, distributed log file. 

Quick Layout Vs Layout (LVL) points out the location of differences, not the exact differences. 

DCV Analyzer tool serves as a starting point for analyzing the performance and hierarchy of an IC Validator run. 

Learn how to run Design Rule Checks (DRC) interactively from IC Validator VUE interface. 

Learn how to select/unselect rules functions in IC Validator within the rule deck file. 

Debugging a runset is a tedious cycle of analyzing output and manually writing out intermediate layers and isolating problems. 

 

IC Validator Layout Vs Layout (LVL) utility compares two layout files and flags the differences between them. 

Learn how to compare DRC results using the IC Validator  DCV Results Compare Tool (RCT) tool.

LVS Videos

Learn how to run Layout-Versus-Schematic (LVS) using IC Validator tool from your shell.

Learn how to run Layout -Vs-Schematic interactively using IC Validator VUE. 

Learn how to run only extraction or only compare in IC Validator LVS flow. 

Learn how to create an equivalence file for LVS run. 

Learn how to use Edtext file in IC Validator.

LVS Black Box flow allows you to validate top-level designs before all of the building blocks in a top chip level are not completed. 

NetTran is a netlist translation utility. 

Learn how to compare two netlists of any format like SPICE, IC Validator or VERILOG using NVN utility. 

Learn how to compare LVS results using IC validator  DCV results compare tool (RCT).

Fill Videos

Learn how to execute fill in IC Validator.

Synopsys Videos and Tech Talks

Fusion Technology: Broadly Addressing the Challenges of 5-nm-and-Below Processes

Architected to extract maximum process entitlement for 5-nm-and-beyond processes’, Synopsys’ latest Fusion Technology is helping customers realize optimal full-flow, power, performance and area while accelerating their ever-important time-to-market.

How to Minimize the Impact of Metal Fill on Timing?

Metal fill insertion affects timing because of added capacitance. Balancing density requirements and timing on critical nets is crucial for timely design closure. IC Compiler II In-Design with signoff quality IC Validator metal fill minimizes the timing impact of metal fill and reduces overall design turnaround time.

How to Reduce the Amount of Time to Fix DRCs Near Tapeout?

In the later stages of design cycle, it is important to identify and fix DRC issues quickly to meet the tapeout schedule. This video discusses some techniques and best practices. Taking advantage of the integration of the IC Compiler II with signoff quality IC Validator DRC checking, designers can automatically fix DRC violations and improve turnaround time by automatically detecting changed ECO areas for incremental DRC checking.