Fusion Technology

Fusion Technology

Fusion Technology™ redefines conventional EDA tool boundaries across synthesis, place-and-route and signoff, sharing integrated engines across the industry’s premier digital design products.  It enables  designers to accelerate the delivery of their next-generation designs with the industry-best quality-of-results (QoR) and the fastest time-to-results (TTR).

Best-in-Class Optimization + Industry-golden Signoff

It redefines conventional EDA tool boundaries across synthesis, place-and-route and signoff, sharing engines across the industry’s premier digital design products, and a unique, single data model for both logical and physical representation. Fusion Technology enables one DNA backbone across the Synopsys Design Platform that includes IC Compiler™ II, Design Compiler® Graphical, PrimeTime®, StarRC™, IC Validator, DFTMAX™, TetraMAX® II, and Formality® tools. It provides ECO Fusion, Signoff Fusion, and Test Fusion, resulting in the most predictable RTL-to-GDSII flow with the fewest iterations, as well as unsurpassed design frequency, power, and area.

"We believe Synopsys’ Fusion Technology is a game-changing innovation in the semiconductor industry, and it will certainly help Samsung Foundry, as well as our customers, to bring innovative products to market more quickly." 

-Jaehong Park, senior vice president, ASIC & IP Team at Samsung Electronics

Achieve Optimal PPA Results, Faster

  • Signoff Fusion drives faster signoff closure by bringing PrimeTime static timing analysis, StarRC extraction, PrimePower, and RedHawk™ Analysis Fusion golden-signoff analysis natively inside IC Compiler II, improving flow predictability. Using PrimeTime’s golden-signoff backbone eliminates the need for excessive design margin and over-constraining for both optimization and signoff enabling perfect correlation, reduced pessimism, and superior QoR for both optimization and signoff.
  • ECO Fusion builds on the fused signoff capabilities by reducing the need for excessive ECO iterations by allowing rapid design changes during the physical implementation phase with IC Compiler II, resulting in faster timing convergence and reducing the design cycle by up to 30%.
  • Test Fusion is the combination of design-for-test (DFT) RTL analysis and DFT synthesis integrated into implementation, enabling best QoR while reducing silicon test costs and turnaround time.
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The Choice of Transistor Architecture for the 5nm Node and Beyond

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Platform-Wide Innovations to Meet the Challenges of 5nm and Beyond