Fusion Technology transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff analysis, enabling designers to accelerate the delivery of their next-generation designs with the industry-best full-flow quality-of-results (QoR) and the fastest time-to-results (TTR).
It redefines conventional EDA tool boundaries across synthesis, place-and-route and signoff, sharing engines across the industry’s premier digital design products, and a unique, single data model for both logical and physical representation. Fusion Technology enables one DNA backbone across the Synopsys Design Platform that includes IC Compiler™ II, Design Compiler® Graphical, PrimeTime®, StarRC™, IC Validator, DFTMAX™, TetraMAX® II, and Formality® tools. It provides Design Fusion, ECO Fusion, Signoff Fusion, and Test Fusion, resulting in the most predictable RTL-to-GDSII flow with the fewest iterations, as well as unsurpassed design frequency, power, and area.
-Jaehong Park, senior vice president, ASIC & IP Team at Samsung Electronics