Wednesday, October 14, 2020
John Busco, Director of Logic Design Implementation, Nvidia
Driven by a thriving high-performance-compute (HPC) market, the unbound growth of the AI and analytics-automation sectors, and the quest to accelerate the broad availability of fully-autonomous automotive platforms, the demands on GPUs are trending exponentially. Given increasingly challenging processing densities coupled to ever constrained thermal design points, there exists a constant need for innovation, not only in the architectural space but also in the tools and optimization methodologies that help to realize these complex SoCs. In this talk, NVIDIA will discuss the logical and physical challenges inherent in the realization of high-performance and market-shaping GPU designs. They will share how they continue to innovate to mitigate shrinking-process-related challenges and outline how, with the help of Synopsys and Fusion Compiler, they are steadfastly achieving the optimum performance-per-Watt while also hitting aggressive market windows.
Shobana Palanisamy, Design Engineer, Arm
Increased mobile-compute performance needs – driven by new applications, experiences, and use cases – demands innovation to address growing design sizes within either constant or shrinking, time-to-market schedules. Arm® and Synopsys, long-time collaborators on advanced design flows, have co-developed state-of-the-art, hierarchical methodologies for the latest and next-generation of processor cores. In this session, Arm will provide insight into the unique challenges of realizing the best power, performance, and area (PPA) targets in the context of a hierarchical design flow, focusing on the newly released Cortex-X1 and upcoming, advanced client processors. Arm will share details of the extensive collaborative work and the resulting flows and methodologies, that mutual customers have already deployed, to realize significant runtime reductions while co-achieving market-shaping performance.
Godwin Maben, Synopsys Scientist, Synopsys
Low power, energy-efficient SoC design requires accurate analysis of dynamic power and the ability to satisfy key power constraints starting from RTL, throughout implementation, and leading to power signoff. This session highlights the key Synopsys digital implementation and signoff technologies enabling designers throughout the Synopsys low power flow.
Sudhir Chandel, Sr. Manager ASIC Design, Synaptics
With an increase in complexity and size of designs, it's hard to find the right activity window for IR-drop analysis. The full FSDB activity file needed for peak power analysis has thousands of cycles and IR-drop tools may not handle them efficiently. This presentation will show how these issues were addressed during the development of a next-generation Synaptics IoT SoC by using Synopsys PrimePower to create a more efficient flow.
Dhiraj Mallick, VP, Engineering and Business Development, Cerebras Systems
AI has massive potential, but it is profoundly compute-intensive. Accelerating AI compute for deep learning requires a powerful processor, optimized to handle the peta-exa scale compute, high bandwidth low latency communication, and tightly coupled memory requirements. In this session, Cerebras will discuss their multi-trillion transistor AI processor chip for deep learning - Wafer Scale Engine (WSE) and highlight innovative solutions from Synopsys that enabled them to bring this ground-breaking SoC to market.
Jimmy Kim, SoC Methodology Engineer, Samsung
As chip designers constantly push the performance, power and area (PPA) envelope against a tight schedule for their next-generation products, innovation in design tools and methodologies have become vital to addressing the mounting process and design related challenges while still maximizing PPA benefit and productivity. In recent years, machine learning (ML) has emerged as a powerful technology, providing EDA developers a new arsenal of solutions for today’s demanding semiconductor design environment. In this session, Samsung shares their experience in leveraging machine learning technologies in Synopsys IC Compiler II to achieve breakthrough quality of results.
Thomas Koch, Sr. Principal Engineer, NXP Semiconductors
Functional safety (FuSa) designs for automotive require redundant structures such as TMR (triple mode redundancy) flip flops to provide reliability and immunity from failures due to random soft errors, such as those that come from alpha particles. Increased SoC functionality requires multitudes more TMRs which not only adds significantly more runtime; but, also makes the complex task of checking many rules and ISO26262 compliance during implementation even more difficult. NXP will present how they are using Synopsys native automotive solutions to insert these redundant type of safety mechanisms in their implementation flow.
Jamileh Davoudi, Sr. Staff Product Marketing Manager, Synopsys
This presentation will show how Synopsys TestMAX FuSa uses static analysis early in the design flow either at RTL or Gate netlist to calculate ISO 26262 metrics such as Single Point Fault Metric (SPFM) and Diagnostic Coverage. TestMAX FuSa identifies blocks in the design that have the highest probability of causing functional safety failure and provides a prioritized list of registers with the largest contribution to single point failure. This list can be then used as a guide for inserting error-tolerant equivalents or Triple Module Redundancy registers in the implementation to achieve the target ASIL.
Fadi Maamari, Group Director, R&D, Synopsys
Synopsys has pioneered synthesis based test, achieving high-quality test as well as optimal design power, performance and area (PPA). The growing need to deliver full production test while maintaining design PPA has spurred new technologies to ‘shift-left’, or verify major design-for-test earlier. These technologies will be covered in this session of Synopsys’ state-of-the-art flow feature TestMAX Manager. In addition, to accelerate understanding of silicon defects that delay the time to full production, multiple new technologies for silicon diagnostics will be discussed. All technologies are key to getting high yield and high-quality test programs in place faster than before.
Bala Tarun Nelapatla, Staff Manager, Solutions, Synopsys
With growing design complexity, the need to minimize test costs and test cycles has become critical. Data center, AI, and GPU designs consisting of hundreds of millions of instances require new compression technologies beyond what has become mainstream. This presentation will cover next generation sequential compression architecture built on already-deployed technology. Key aspects of this state-of-the-art compression architecture will be covered, followed by the corresponding pattern generation results and their improvement vs other compression architectures.
Randy Fish, Director of Marketing, Synopsys
The Synopsys Silicon Lifecycle Management (SLM) platform uses extensive silicon device data and targeted analytics to greatly improve how chips and systems are designed, manufactured, deployed and maintained in the field. The SLM platform is tightly coupled to Synopsys’ implementation, signoff and test solutions and incorporates embedded instrumentation IP along with analytics software. This enables new levels of insights for SoC teams and their customers and the ability to optimize operational activities at each stage of a device throughout its life.
Pascal Sotiaux, Engineering Leader and Test Support Manager, STMicroelectronics
The increasing complexity of design, manufacturing and test is resulting in an overwhelming amount of data. The ability to systematically analyze and effectively detect quality and yield issues is becoming virtually impossible with traditional tools and methods. This situation is compounded by the need to detect, prevent, predict and control the process in real time throughout the supply chain. The need to bridge the gap between analytics and action has dramatically grown. This presentation shows how Silicondash improves engineering and operations efficiency, thus enabling collaboration between the supply chain participants to make informed decisions and improve the critical operational KPIs.