Digital Design Technology Symposium

October 14, 2020
9:00 a.m. - 1:30 p.m. PDT
Virtual Experience

A Must-Attend Event

HPC, 5G, mobile, automotive, AI: these are the technology segments that are bringing new design challenges to ASIC and SoC designers. For the past two years, Synopsys has been hard at work delivering a continuous stream of innovative products with future-proof technologies to address ultra-low power design, exploding design sizes and signoff scenarios, functional safety, security, and yield optimization. The Digital Design Technology Symposium is an event that showcases Synopsys’ digital design solutions.

With something of interest for a broad range of market segments, drop in and see how Synopsys’ innovative solutions can help with your next design. Whether you are targeting improved power, performance and area, yield, time-to-market or all of the above, recent advances in Synopsys’ Fusion Design Platform solutions can help you meet your digital design goals. You will gain new insights from Synopsys R&D experts, users, and partners on integrated, end-to-end solutions being used to achieve industry leading QoR and productivity in key areas. 


Who Should Attend?

Digital design managers/directors, and engineers working on their next SoC or ASIC. Especially those challenged by requirements in the HPC, 5G, mobile, automotive, and AI market segments.  CAD managers/directors looking to integrate the latest design innovations into their in-house design flows to boost design team productivity and improve design quality. Senior level engineering management wanting to understand where Synopsys is headed and why they should invest long term in Synopsys design solutions.


Keynotes Spotlight

Wednesday, October 14, 2020

Running with the Bulls: Synopsys Innovations to Address the Next Wave of Design Challenges

Wednesday, October 14 | 9:00 AM PDT


With semiconductors fueling much of the ”Smart Everything” revolution, EDA has been front-and-center in the spotlight as a key enabler for continuing density, performance and performance-per-watt improvements. The challenges faced by advanced node designers include timely enablement, full-flow throughput, end-to-end power optimization and multi-die integration to name a few. In addition, AI hardware accelerators are driving strong interest in domain specific architectures and the need for rapid RTL exploration with accurate power, performance and area  (PPA) measurements. Looking ahead, AI/ML and Cloud open up several new innovations in the EDA space to optimize and accelerate EDA flows. With functional safety, reliability and security concerns paramount in mission-critical applications, design flows need to natively represent these careabouts without compromising design PPA goals. In his presentation, Shankar will review the latest innovations in Synopsys’ Fusion Design Platform to address these challenges and opportunities.

Shankar Krishnamoorthy
General Manager, Digital Design Group
Synopsys
Sriram Satakopan
VP Engineering
NXP Semiconductors

Cost, Differentiation and Time-to-Market: How Hyperconvergence in EDA is Helping Solve Key Business Growth Imperatives

Wednesday, October 14 | 9:25 AM PDT

To execute successfully in critical market segments such as automotive, industrial & IoT, mobile and communications infrastructure requires a laser focus on differentiation, cost and time to market. Increasing complexity as the transition is made to advanced process nodes requires a redefinition of the SoC development flow to substantially lower project cycle times and increase engineering efficiency. Parallel execution is critical to meeting 10-week cycle times and addressing the challenges faced with a 6x increase in instances per square millimeter. Many metrics of engineering efficiency need to be monitored and improved as design complexity increases and fewer engineering resources are available. These challenges are driving the need for a highly convergent, vertically integrated digital design solution that delivers predictable quality of results together with faster turnaround times. Learn more about the SoC design challenges being faced and how these are being addressed today.


Breakout Sessions

Wednesday, October 14, 2020

Agenda-At-A-Glance

HPC and Advanced Technology

10:00 - 10:20 AM

Delivering NVIDIA’s Next-Generation GPUs for High-Performance-Computing

John Busco, Director of Logic Design Implementation, Nvidia

Driven by a thriving high-performance-compute (HPC) market, the unbound growth of the AI and analytics-automation sectors, and the quest to accelerate the broad availability of fully-autonomous automotive platforms, the demands on GPUs are trending exponentially. Given increasingly challenging processing densities coupled to ever constrained thermal design points, there exists a constant need for innovation, not only in the architectural space but also in the tools and optimization methodologies that help to realize these complex SoCs. In this talk, NVIDIA will discuss the logical and physical challenges inherent in the realization of high-performance and market-shaping GPU designs. They will share how they continue to innovate to mitigate shrinking-process-related challenges and outline how, with the help of Synopsys and Fusion Compiler, they are steadfastly achieving the optimum performance-per-Watt while also hitting aggressive market windows.

10:20 - 10:40 AM

Hierarchy-Methodology Innovation for Advanced Arm® Cores

Shobana Palanisamy, Design Engineer, Arm

Increased mobile-compute performance needs – driven by new applications, experiences, and use cases – demands innovation to address growing design sizes within either constant or shrinking, time-to-market schedules. Arm® and Synopsys, long-time collaborators on advanced design flows, have co-developed state-of-the-art, hierarchical methodologies for the latest and next-generation of processor cores. In this session, Arm will provide insight into the unique challenges of realizing the best power, performance, and area (PPA) targets in the context of a hierarchical design flow, focusing on the newly released Cortex-X1 and upcoming, advanced client processors. Arm will share details of the extensive collaborative work and the resulting flows and methodologies, that mutual customers have already deployed, to realize significant runtime reductions while co-achieving market-shaping performance.

10:40 - 11:00 AM

Stunning Graphics in the Palm of Your Hand

Prayag Patel, Sr. Director of Engineering, Qualcomm

Mobile gaming, projected to generate over $75B in 2020 alone, is now, by far and away, the dominant gaming platform after surpassing both the standalone console and PC markets since 2018. While sharing the same user-focused challenges as other platforms – delivering ultra-sophisticated graphics at ultra-high frame rates – the mobile space bears numerous unique challenges, including hyper-constrained form factors and limited energy capacity. In this session, Qualcomm Technologies — a longtime mobile-gaming pioneer — will share how they are efficiently mapping Fusion Compiler’s leading power, performance, and area metrics, into better battery life, class-leading frame rates, all in a pocket-sized experience. Efficiently turning premium mobile devices into serious gaming machines.

Low Power

11:15 - 11:35 AM

Synopsys SW-Driven Low Power Design Solution

Godwin Maben, Synopsys Scientist, Synopsys

Low power, energy-efficient SoC design requires accurate analysis of dynamic power and the ability to satisfy key power constraints starting from RTL, throughout implementation, and leading to power signoff. This session highlights the key Synopsys digital implementation and signoff technologies enabling designers throughout the Synopsys low power flow.

11:35 - 11:55 AM

Finding the Right Cycles: Efficient Power Analysis and IR Profiling for Next Generation IoT SoC Using PrimePower

Sudhir Chandel, Sr. Manager ASIC Design, Synaptics

With an increase in complexity and size of designs, it's hard to find the right activity window for IR-drop analysis. The full FSDB activity file needed for peak power analysis has thousands of cycles and IR-drop tools may not handle them efficiently. This presentation will show how these issues were addressed during the development of a next-generation Synaptics IoT SoC by using Synopsys PrimePower to create a more efficient flow.

11:55 - 12:15 PM

Improving Early Power Estimation Accuracy When Using Fusion Compiler

Anshul Bansal, Hardware Engineer, Microsoft

Early estimation of power accuracy is key for identifying power critical blocks in the design and modifying RTL to improve power. In this presentation, we cite the reasons, issues and a methodology for dealing with the lack of accuracy in early power estimation. Using PrimePower with Fusion Compiler, we analyze methodologies to avoid the sources of inaccuracy to provide an accurate power estimate which can be used for averaged or time-based analysis flows. We will also share optimization and analysis results to achieve accurate early power analysis to achieve better quality of silicon when using these tools.

Machine Learning/AI

12:30 - 12:50 PM

Designing Wafer Scale SoC for AI Compute Acceleration Using Synopsys Digital Design Solutions

Dhiraj Mallick, VP, Engineering and Business Development, Cerebras Systems

AI has massive potential, but it is profoundly compute-intensive. Accelerating AI compute for deep learning requires a powerful processor, optimized to handle the peta-exa scale compute, high bandwidth low latency communication, and tightly coupled memory requirements. In this session, Cerebras will discuss their multi-trillion transistor AI processor chip for deep learning - Wafer Scale Engine (WSE) and highlight innovative solutions from Synopsys that enabled them to bring this ground-breaking SoC to market.

12:50 - 1:10 PM

Enabling Next-Generation SoC Design with Machine-Learning Driven Implementation

Jimmy Kim, SoC Methodology Engineer, Samsung

As chip designers constantly push the performance, power and area (PPA) envelope against a tight schedule for their next-generation products, innovation in design tools and methodologies have become vital to addressing the mounting process and design related challenges while still maximizing PPA benefit and productivity. In recent years, machine learning (ML) has emerged as a powerful technology, providing EDA developers a new arsenal of solutions for today’s demanding semiconductor design environment. In this session, Samsung shares their experience in leveraging machine learning technologies in Synopsys IC Compiler II to achieve breakthrough quality of results.

1:10 - 1:30 PM

Building the Next Generation Multi-Billion Gate Intelligence Processing Unit with Synopsys Implementation Tools

Phil Horsefield, VP, Silicon, Graphcore

AI chip architectures demand massively replicated processing unit topologies to meet the high parallel processing requirements of data centers. Due to this requirement, the design sizes are very large, with stringent power & area targets and aggressive compute performance goals. Building the next generation AI processor requires a scalable solution that can manage thousands of replicated blocks and optimize power throughout the flow without compromising on the performance metrics. In this session, Graphcore will talk about the successful design and tape-out of their next generation Colossus MK2 IPU utilizing the Synopsys Digital Implementation Platform which includes AI-centric optimization technologies such as logic restructuring, congestion-driven mux optimization and full-flow concurrent clock and data optimization.

FuSa Automation

10:00 - 10:20 AM

Efficient FuSa Implementation of TMR Using Synopsys Native Automotive Solutions

Thomas Koch, Sr. Principal Engineer, NXP Semiconductors

Functional safety (FuSa) designs for automotive require redundant structures such as TMR (triple mode redundancy) flip flops to provide reliability and immunity from failures due to random soft errors, such as those that come from alpha particles. Increased SoC functionality requires multitudes more TMRs which not only adds significantly more runtime; but, also makes the complex task of checking many rules and ISO26262 compliance during implementation even more difficult. NXP will present how they are using Synopsys native automotive solutions to insert these redundant type of safety mechanisms in their implementation flow.

10:20 - 10:40 AM

Fast, Early and Cost-Effective Functional Safety Analysis

Jamileh Davoudi, Sr. Staff Product Marketing Manager, Synopsys

This presentation will show how Synopsys TestMAX FuSa uses static analysis early in the design flow either at RTL or Gate netlist to calculate ISO 26262 metrics such as Single Point Fault Metric (SPFM) and Diagnostic Coverage. TestMAX FuSa identifies blocks in the design that have the highest probability of causing functional safety failure and provides a prioritized list of registers with the largest contribution to single point failure. This list can be then used as a guide for inserting error-tolerant equivalents or Triple Module Redundancy registers in the implementation to achieve the target ASIL.

10:40 - 11:00 AM

Samsung Foundry’s Automotive Reference Flow

Eunju Hwang, Staff Engineer, Samsung Foundry

Automobiles must operate in a safe, reliable and secure manner, especially in next-generation autonomous driving and advanced driver-assistance systems (ADAS) applications. E/E systems in such vehicles, such as SoC designs, should comply with the ISO 26262 standard to achieve functional safety which is specified by automotive safety integrity level (ASIL). Samsung Foundry will present how their automotive reference flow is using Synopsys’ comprehensive automotive solutions to help their customers meet their target ASILs.

Test Innovations

11:15 - 11:35 AM

TestMAX Shifts Left: Earlier DFT Verification and Speed-Up of Silicon Diagnostics

Fadi Maamari, Group Director, R&D, Synopsys

Synopsys has pioneered synthesis based test, achieving high-quality test as well as optimal design power, performance and area (PPA). The growing need to deliver full production test while maintaining design PPA has spurred new technologies to ‘shift-left’, or verify major design-for-test earlier. These technologies will be covered in this session of Synopsys’ state-of-the-art flow feature TestMAX Manager. In addition, to accelerate understanding of silicon defects that delay the time to full production, multiple new technologies for silicon diagnostics will be discussed. All technologies are key to getting high yield and high-quality test programs in place faster than before.

11:35 - 11:55 AM

Achieving Higher Compression for Complex Designs: Sequential Compression

Bala Tarun Nelapatla, Staff Manager, Solutions, Synopsys

With growing design complexity, the need to minimize test costs and test cycles has become critical. Data center, AI, and GPU designs consisting of hundreds of millions of instances require new compression technologies beyond what has become mainstream. This presentation will cover next generation sequential compression architecture built on already-deployed technology. Key aspects of this state-of-the-art compression architecture will be covered, followed by the corresponding pattern generation results and their improvement vs other compression architectures.

11:55 - 12:15 PM

Multithreaded Chain Diagnosis for Complex SoC in Advanced Technologies

Nelly Feldman, Diagnosis Engineer, STMicroelectronics

This presentation describes STMicroelectronics methodology for chain diagnosis analysis for complex SoC in presence of multiple defective chains. In the presentation, we provide a flow based on multithread approach and practical examples for chain diagnosis analysis that minimize the run time while improving the accuracy and precision for multiple chain defects.

Silicon Lifecycle Management

12:30 - 12:50 PM

Silicon Lifecycle Management Enables Deep Insight for Electronic System Creation and Operation

Randy Fish, Director of Marketing, Synopsys

The Synopsys Silicon Lifecycle Management (SLM) platform uses extensive silicon device data and targeted analytics to greatly improve how chips and systems are designed, manufactured, deployed and maintained in the field. The SLM platform is tightly coupled to Synopsys’ implementation, signoff and test solutions and incorporates embedded instrumentation IP along with analytics software. This enables new levels of insights for SoC teams and their customers and the ability to optimize operational activities at each stage of a device throughout its life.

12:50 - 1:10 PM

Engineering and Operations Efficiency Improvement When Using Silicondash

Pascal Sotiaux, Engineering Leader and Test Support Manager, STMicroelectronics

The increasing complexity of design, manufacturing and test is resulting in an overwhelming amount of data. The ability to systematically analyze and effectively detect quality and yield issues is becoming virtually impossible with traditional tools and methods. This situation is compounded by the need to detect, prevent, predict and control the process in real time throughout the supply chain. The need to bridge the gap between analytics and action has dramatically grown. This presentation shows how Silicondash improves engineering and operations efficiency, thus enabling collaboration between the supply chain participants to make informed decisions and improve the critical operational KPIs.

1:10 - 1:30 PM

Chasing 7nm Yield Entitlement with Yield Explorer

Jason (JT) Scott, Senior Member Technical Staff, Advanced Micro Devices

Product cycle times are tight and margins are even tighter. In the world of high volume semiconductors, determining whether a design is a winner or loser is sometimes decided in the backend. Fabless yield engineering teams partnering with their foundries, work to influence whether the ink on the quarterly report is red or black.


A Must Attend Event

You will gain new insights on the latest Synopsys Digital Design Solutions:

  • Machine Learning/AI
  • Low Power
  • FuSa Automation
  • HPC & Advanced Technology
  • Test Innovations
  • Silicon Lifecycle Management