Modeling environments are popular for algorithm design and exploration because they allow concise representations of behavior at very high levels of abstraction. These environments provide sophisticated design capture, simulation and analysis tools for multiple domains. However, problems arise when the designer needs to translate the design intent into their RTL counterparts for use with ASIC or FPGA implementation tools. In particular, traditional methods have proven to be very time consuming and/or prone to error because of re-coding and re-verification into the RTL domain. The Synphony Model Compiler high-level synthesis solution addresses these problems by providing an easy and automated method to synthesize electronic system-level algorithmic representations from the Simulink / MATLAB model-based design environment.