Verification Day 2021

A Virtual Event
September 28-29, 2021

Why Attend?

This virtual event provides an opportunity to stay informed about the latest innovations, techniques and methodologies in verification hardware and software. This 2-day event will share experiences and insights from users solving tough verification challenges using Synopsys solutions.

This year’s event will have a special focus on technology trends and case studies spanning simulation, static, formal, low power, VIP, emulation, and virtual prototyping. Attendees will leave with practical information to accelerate verification closure. 

Presentation Tracks

Formal Verification

Exploring methods to find and fix bugs early

Static Verification

Analyzing designs for correct construction, clock and reset domain crossings

Architecture to Software

Defining and implementing complex SoCs with functionality-defining Software

Debug for Design & Verification

Examining and solving the most complicated SoC debug problems

High-Performance Simulation & VIP

Creating high-quality designs through accelerated runtime and debug for timely coverage convergence

Low Power

Addressing power challenges with breakthrough performance for hardware and software power verification

Keynote Spotlight

Kailash Gopalakrishnan

IBM Fellow and Sr. Manager, Accelerator Architectures and Machine Learning, IBM

September 28, 2021 | 9:30 - 10:00 AM PT

AI Hardware and the Implications on Design, Verification and Software

Innovations in architecture, low-precision arithmetic and analog computing are driving up the performance and power-efficiency of purpose-built AI hardware to the Petaflop range for both Inference and Training systems. Integrating these purpose-built chips within large scale data-centers also drives the incorporation of virtualization and security features in hardware in addition to these core AI capabilities. In this talk, I'll describe some of the key challenges in building these complex AI chips from a design, verification and software perspective. I'll also highlight some of the key advances and hardware opportunities for AI systems in the decade ahead.

 

David Lacey

Chief Verification Scientist, Hewlett Packard Enterprise

September 29, 2021 | 9:30 - 10:00 AM PT

Growing Your Team’s VLSI Design and Verification Methodologies to Meet Modern Chip Design Challenges

The cost of tape releases continues to skyrocket, driving businesses to ensure their designs are production worthy on first silicon.  This creates a demand to modernize the VLSI development methodologies used by teams.  We will dive into the opportunities that exist today for VLSI teams to keep up with their own development modernization demands.  We will explore opportunities for all teams, from simple steps such as advancing coverage capabilities and utilizing mature EDA features such as save and restore to more powerful techniques such as advanced data analytics, formal proofs, emulation, and machine learning.  Finally, we will touch on how to modernize your compute environments.  Each of these steps will allow any team to better meet its chip design challenges as it strives for first-time-right silicon.

Tracks & Sessions

Day One: Tuesday, September 28

Formal + -

10:00 - 10:30 AM PT

Leveraging Formal Equivalence for Datapath and Clock Gating Logic Verification

Di Wu, ASIC Engineer, Facebook
Prashant Kumar, Sr. Applications Engineer, Synopsys

There are many complex verification problems to overcome for a successful design tapeout. Two such problems, which are extremely hard to solve, are datapath validation and clock gating logic verification. These problems need to cover a tremendously large state space which is nearly impossible to verify using traditional simulation based methods. In this presentation, we describe the need to exhaustively verify the datapath of a custom IEEE 754 floating point unit with a slight variation from the standard. We also show how we proved the functional correctness of the design in the presence of clock gating logic with VC Formal. We applied formal sequential equivalence checking (SEQ) and it significantly helped increase our confidence. One challenge was the large number of non-resettable blocks and we found a solution to abstract the constraints and apply them to multiple blocks, without over constraining the designs. We will also describe the approach taken to generate the results on an accelerated time schedule.

10:30 - 11:00 AM PT

AI/ML Enabled Formal Signoff Success at Samsung SLSI

Jiyong Ahn, Staff Engineer, Samsung

With formal technology becoming an integral part of the verification flow, there is rising demand for faster completion of block verification and the need for signoff measurement. Although formal is known for exhaustive proofs of individual properties and ability to flush out corner case bugs, there is a need for comprehensive measurement on verification completeness. Also, IP verification is an iterative process which consumes resources and time. Samsung has many years of history applying formal technology in the verification flow using legacy solutions. In this presentation, Jiyong shares how his team was able to accelerate formal verification with AI/ML using the VC Formal Regression Mode Accelerator (RMA) App and achieve even higher confidence with RTL mutation analysis using the FTA (Formal Testbench Analyzer) App.

11:10 - 11:40 AM PT

Enhancing IP/SoC Quality by Augmenting Formal Verification

Vaibhav Kumar, Senior Manager IP Verification, NXP Semiconductors
Mitul Vaghani, Senior Design Engineer, NXP Semiconductors

The application of formal verification can help find corner-case bugs. There is a wide spectrum of formal apps which help reduce effort on the user side and provide high ROI. One example is to find the basic issue of arithmetic overflow, full case and parallel case which can often lead to different simulation results pre/post synthesis. Another example is functional safety which is an important aspect of automotive solutions. Failure to find corner case bugs can lead to violation of safety goal for ASIL compliance. This is where formal bug hunting can be very effective. NXP has been deploying formal for end-to-end signoff of some of the glue logic (SoC Specific Logic) which is suitable to be stressed through formal techniques. In this presentation, we will share a case study on how VC Formal was used for exhaustive verification and signoff of a AHB gasket block.

11:40 - 12:10 PM PT

Expanding the Footprint of Formal By Finding New Avenues for Post Silicon Bug Validation and Datapath Verification

Anshul Jain, Formal Verification Engineer, Manager, Intel
Disha Puri, Formal Verification Engineer, Manager, Intel

Formal verification (FV), as a technology, has grown beyond its immediate applications of formal property verification and exhaustive datapath checks. The Formal Verification Central Tech Office (FVCTO) at Intel explored some of the extended use cases and provided a set of recommendations and results on these applications. In this presentation, we explain two parallel high ROI implementations of FV technology. We will discuss how VC Formal can be leveraged to reproduce and confirm the theory of post silicon bug, validate the late bug fix through an exhaustive list of scenarios to mitigate the risk, evaluate the workarounds and provide high confidence bug fix avoiding re-spins. Additionally, we will also illustrate how to leverage the C2RTL formal equivalence technology to prove the specification in C and further scale the application to RTL2RTL equivalence on data intensive blocks.

12:10 - 12:40 PM PT

Filling the Coverage Holes of Functional Verification using Formal Coverage API

Gaurav Dwivedi, Senior Engineer, Qualcomm
Deepak Agarwal, Engineer, Qualcomm
Saurabh Shrimal, Principal Engineer, Qualcomm

Design Verification closure with 100% code and functional coverage is challenging due to increased design complexity and schedule constraints. Identification of wide variety of scenarios followed by developing directed tests to fill code coverage holes for conditions and FSMs deep down in the design hierarchy is near impossible for achieving verification closure for huge designs. It is vital to identify unreachable cover bins, FSM states and conditions early to save the critical time. In this presentation, we'll discuss our final signoff approach using VC Formal to identify the unreachable paths in the design and pinpoint the valid scenarios to fill the rest of coverage holes by simulation based functional verification.

Static + -

10:00 - 10:30 AM PT

Clock Domain Crossing Verification Using ML Based Root Cause Analysis

Francis Chockalingam, Master Engineer, Broadcom

Having multiple, hierarchical power and clock domains enables systems to achieve the optimal power-performance threshold. However, the verification of such complex SoCs poses a great challenge be it simulation or static verification. This presentation details how VC SpyGlass CDC hierarchical flow was leveraged for verification of a large SoC targeting a Machine Learning application with 127 clocks in 84 asynchronous clock domains. The presentation discusses the various techniques, including ML-based Root Cause Analysis, used for addressing the noise reduction and achieving faster debug using violation clusters.

10:30 - 11:00 AM PT

Efficient Improvement of FPGA Quality with VC SpyGlass Lint and CDC

Ryan-HC Yang, Engineer, Mediatek

The lack of support for specific settings raises enormous challenges for running Lint/CDC flow for FPGA-based designs resulting in design issues escaping to a much later ProtoCompiler (UCPC) stage. This leads to many long iterations and expensive delays. In this presentation, we will showcase how FPGA integrator can find design issues early by using Synopsys VC SpyGlass thereby avoiding iterations and fast track project schedules. We also discuss how VC SpyGlass runs can be customized flexibly allowing the integrator to make necessary changes in relevant Lint/CDC rules.

11:10 - 11:40 AM PT

Static Verification Challenges and Learnings from Complex SoC Development

Clarke Watson, Chip Lead, Facebook

Complex SoCs bring an altogether different set of challenges for designers, way beyond the typical static verification. In this presentation, we will cover the complex SoC environment with multi-level abstractions and the challenges it exposes for static verification. In addition, we will talk about our learnings (Do’s and Don’ts) from the execution of successful SoC tapeouts. This presentation will cover specific aspects of Lint, CDC and RDC methodologies and associated debug practices.

11:40 - 12:10 PM PT

Scaling Netlist CDC Verification with Hierarchical and Machine Learning with VC SpyGlass CDC

Pratik Porwal, ASIC-PD Methodology Team Member, NVIDIA
Alex Li, ASIC-PD Methodology Team Member, NVIDIA

In this presentation, we will share details on the need of Netlist CDC verification for signoff and the challenges it brings, especially at billion plus Netlist scale. We will talk about how Machine Learning and Hierarchical CDC helped us to scale our verification for debug and improved our productivity with VC SpyGlass CDC.

12:10 - 12:40 PM PT

Challenges and Solutions for Cross Domain Analysis for MBIST-inserted RTL

Wesley Lee, Staff GPU Integration Engineer, Samsung
Aditya Vummannagari, GPU Integration Lead, Samsung

During MBIST insertion logic design undergoes significant changes that may introduce a substantial number of new Clock Domain Crossing (CDC) paths on top of already CDC clean RTL rendering CDC signoff of MBIST inserted RTL crucial. This presentation focuses on the analysis, challenges and solutions for MBIST-inserted RTL and showcases the approach for successful signoff using VC SpyGlass CDC. The presentation will also provide a brief overview of the MBIST-inserted components, their impact on overall CDC violations, and the constraints required to counter these design changes. The presentation will conclude with analysis of the results and issues that were encountered.

10:00 - 10:30 AM PT

Joint SoC Architecture Exploration and RTL Performance Verification to Achieve Rapid SoC Chassis Turnaround

Piyush Singh, Senior Engineering Consultant - SoC Architecture, Sondrel

Sondrel’s concept of an SoC “Chassis” essentially encapsulates all common IP blocks apportioned for a particular SoC usecase. The standard methodology for discovering a Chassis begins with an Architecture Exploration phase using Synopsys Platform Architect Ultra, followed by RTL Performance Verification using a custom Python/SystemC environment built on top of Synopsys VCS and Verdi. However, with RTL generators becoming readily available to generate synthesisable IP, and a desire to achieve rapid design turnarounds, Sondrel has developed a new methodology where RTL Performance Verification begins on Day 1 and runs parallel to Architecture Exploration. This presentation will discuss this approach and how it ensures a substantial and consistent parity of performance metrics between the Virtual Platform and RTL Verification environments, thereby reducing uncertainty and increased early confidence in the success of an SoC project.

10:30 - 11:00 AM PT

Virtualized CPU Usage in SoC Verification

Mika Mäenpää, Verification Engineer SoC/IP, Nokia Networks

The use of virtualized CPUs in SoC verification increases the overall productivity of traditional verification methods. A complete virtual CPU (VCPU) subsystem is implemented and used to improve the performance and enable early application development of a top-level SoC design. In this work, a virtual fast model of a functionally accurate Arm Cortex-A55 microarchitecture is used. The VCPU was compared to an AXI VIP connection, which is a bus functional model of the CPU, to find out differences between traditional verification and co-verification flows. The measurements indicate that co-simulation with VCPU has a very good performance compared to traditional verification methods. We were able to boot Linux on VCPU in 39 seconds. In register accesses, the use of a VCPU was 27% faster in our bare metal test environment, but with the maximum performance, it would be up to 250% faster than an AXI VIP connection. In this presentation we will discuss how Nokia significantly improved the traditional verification cycles by enabling earlier software development and early hw/sw interface testing with the use of virtualized CPUs in Virtualizer.

11:10 - 11:40 AM PT

Real Number Modeling using SV Nettypes

Nihar Veeragandham, Senior Design Engineer, Micron

Communication between the analog SPICE circuitry and its digital counterpart is proving to be a major challenge in verifying complex mixed signal design. To meet tight project schedules engineers typically use Verilog behavioral models with some spice models to improve performance. These Verilog models prohibit the use of Verilog “Real” type in the module I/Os, this restriction forces designers to define the module I/Os as Verilog “wire”. An inter-module analog signal defined using a wire can only resolve to a 0 (grounded signal) or a 1(signal at any other voltage). This loss of this voltage information forces engineers to trace back through the logic cone of this analog signal to verify its voltage value. This loss of data affects both the quality and the efficiency of the simulation. To get around these challenges’ designers need the capability to pass “real” values with very high efficiency. In this presentation we talk about how we leveraged VCS support of SystemVerilog nettypes to describe general abstract values for a net with an optional resolution function to transfer voltage values between analog to digital boundary and vice versa without any loss of resolution.

11:40 - 12:10 PM PT

Accelerating Validation of Next-Generation Cloud Architectures with Virtual Testing

Kinjal Shah, Member of Technical Staff, Pensando Systems, Inc.

Next-generation data center architectures for cloud processing are highly flexible, high-performance systems. To meet performance demands, these architectures must optimally process a high volume of networking traffic to minimize latencies and processing time together with compute and storage resources. Modern network switches are highly programmable to enable optimized cloud processing. The networking system-on-chips (SoCs) at the heart of the data center architectures must go through rigorous pre-silicon validation to ensure they optimally support network traffic. Validation of networking SoCs is very demanding task and only possible with state-of-the-art emulation and tester solutions. In this webinar Synopsys will present how a virtual testing solution using Synopsys ZeBu and Keysight IxVerify tester software enables maximizing validation of realistic network traffic scenarios before silicon is available. Pensando will also share their experience using this solution for the development of one of the most advanced networking SoCs in the industry.

12:10 - 12:40 PM PT

End-to-end Prototyping: Verification to Performance Benchmarking

Praveen Goyal, Principal Engineer, Arm

Traditionally prototyping has been used for IP and/or system validation along with SW Stack development. In this presentation we will show how prototyping can also be used for in-depth verification leveraging all provided debug mechanisms including SystemVerilog assertions (SVAs). We will demonstrate how SVA-based prototyping with the latest HAPS-100 generation reduces time to root cause and reduce debug TAT. We will also share how prototyping use can be extended into performance benchmarking measuring real workloads under real world conditions. We will cover the end-to-end use cases deployed with HAPS-100 from single FPGA IP prototypes through subsystems to entire SoCs mapped to multiple FPGA boards.

Day Two: Wednesday, September 29

10:00 - 10:30 AM PT

Higher Throughput in a Continuous Integration Flow using AI/ML based VCS Dynamic Performance Optimization (DPO)

Vishwanath Gunge, Sr. Hardware Engineer, Microsoft

The integration of multicore CPUs, graphics coprocessors, multimedia, and networking facilities in the SoCs that power today’s sophisticated gadgets is creating a new verification challenge. Exploding chip complexity has added increased verification turn-around-time and compute cost. Microsoft needed a solution that can monitor and auto-tune simulation for better performance without human intervention, helping to reduce performance bottleneck and cost of running an HDL simulation in a complex verification environment. This presentation describes how Microsoft met this need with Synopsys' VCS Dynamic Performance Optimization (DPO) technology. It was used in a continuous integration system to improve verification efficiency, achieve faster gains and minimize overall compute cost and wait times for engineers to check-in their code.

10:30 - 11:00 AM PT

Using AI/ML in VCS to Accelerate Functional Coverage Convergence

Xin Feng, Verification Leader, Allwinner Technology

Functional coverage continues to be the most important metric to gauge verification completeness for tape-out. This presentation describes an AI/ML-based coverage optimization approach with VCS that maximizes resource utilization while potentially shortening the verification schedule. It will illustrate how users can achieve better stimulus generation and higher functional coverage with the VCS Intelligent Coverage Optimization (ICO) technology.

11:00 - 11:30 AM PT

Finding Timing Bugs Earlier in RTL using SDC-aware Simulation

Muhannad Ghanem, Director, Verification, AWS, Annapurna Labs, Amazon
Arik Rachevsky, Principal Applictions Engineer, Synopsys

Until now, designers have relied on gate level simulations to catch chip-killing bugs that other tools like static timing analysis (STA), assertion based verification (ABV), static verification, and emulation couldn’t catch. Gate level simulations can be an extremely expensive effort and it often becomes active only in the very late stages of the design process when the netlist and standard delay format (SDF) files are available. This presentation will highlight Synopsys' VCS verification solution, where design bugs related to timing constraints and exceptions on clocks and resets can be exposed at RTL by analyzing the Synopsys Design Constraints (SDC) file along with the VCS simulation executable. This helps catch these kinds of bugs early in the development process and saves time.

Debug + -

10:00 - 10:30 AM PT

Reclaiming Regression Debug Productivity With Verdi

Lim Han Ying, Staff Design Verification Engineer, MediaTek Singapore Pte. Ltd.
Taruna Reddy, Sr. Product Marketing Manager, Synopsys

In light of the ever-increasing chip design complexity, the explosion in verification challenges ranging from regression size to the scope of debugging are inevitable. An automated solution to perform regression analysis or bug triaging that is integrated with extended debug capability would certainly reclaim most verification productivity, thereby allowing design verification engineers time to perform more valuable verification tasks. In this session, we will explore how Synopsys Verdi with AI/ML can automate tough regression debug challenges like binning and bug triaging.

10:30 - 11:00 AM PT

Root-cause Analysis (RCA) of Unknowns (X) in DFT Verification using Verdi

Ken Li, Engineer, NVIDIA

Tracing unknowns in gate-level simulations (GLS) is an iterative and a manual process, making it highly inefficient. Synopsys Verdi now provides an automated way to alleviate this by tracing unknowns in FSDBs in batch mode, and giving a well-categorized report for root causes. Taking it a step further, Verdi reduces false unknowns introduced by pessimism, letting the user focus on the real unknowns (Xs) in the design. This presentation will discuss how this Verdi XRCA technology effectively debugs the root cause of large amounts of X-value signals.

11:00 - 11:30 AM PT

Easier Root Cause Analysis with Efficient Testbench Debug in Verdi

John Elliott, Senior Staff Engineer, Synopsys

Synopsys Verdi provides root cause analysis solutions for different types of errors (TB, DUT, VIP, IP, SoC). Post-simulation root cause analysis helps find a bug quickly, but sometimes it is still not easy to locate the exact line of code with the bug. This session demonstrates how Verdi can be used to trace the root cause in a VIP-based test environment and find the source code that causes the divergence between the target test and the reference test. This includes differential debug which can help identify the root cause of change in simulation quickly.

Low Power + -

10:00 - 10:30 AM PT

Emulation-Based Power Estimation using ZeBu Empower

Glidden Martin, Technical Lead, Intel

Every generation of SoC design is expected to deliver higher performance while consuming less power. In order to achieve this, it is imperative that each IP meets performance and power goals before getting integrated into the SoC. Otherwise, the optimizations at the IP level may not be addressed on time for the current project. It is also necessary that the tests run on these IPs reflect real workloads that correlate better with post-silicon . Current pre-Si power estimation tools are limited in their ability to handle large collaterals with longer tests and hence the power estimates projected for these IPs may fall far short on silicon. In this presentation we'll discuss how ZeBu Empower has been engineered to scale for IP and SoC level power analysis while leveraging fast emulation of real workloads and how we applied this at Intel.

10:30 - 11:00 AM PT

The New AI Frontier – Breaking Down Power Barriers

Zoreh Azizi, Emulation Engineer, SiMa.ai

AI designs pose unique implementation and verification challenges due to their size and complexity. Ensuring a project is under power budget requires accurate and timely feedback from real software workloads in pre-silicon. This presentation will explain how ZeBu Empower has enabled power analysis for SiMa.ai at SoC level with multiple iterations per day.

11:00 - 11:30 AM PT

ZeBu Empower: Billion Gates Power Analysis Using Emulation

Shirish Kumar Bette, Senior Staff Applications Engineer, Synopsys

Delivering maximum compute performance, ZeBu Empower is the industry’s first and fastest power-aware emulation system for multi-billion gate designs that enables power verification within hours using real-life workloads. Leveraging the best emulation and power calculation engines, ZeBu Empower allows designers to quickly identify power-hungry areas that can improve dynamic and leakage power of the system early on, while meeting fast turnaround time requirements. Synopsys has built unique technology by creating highly scalable and efficient power calculation to ensure both design size and emulation cycles can be parallelized. From an architectural standpoint, this breakthrough innovation allows teams to scale design cycles and tie emulation capabilities unlike ever before. The performance of ZeBu Empower enables multiple iterations per day with actionable power profiling in the context of the full design and its software workload. The ZeBu Empower emulation system also feeds forward power-critical blocks and time windows into Synopsys' PrimePower engine to accelerate RTL power analysis and gate-level power sign-off.

Verification Day 2021 | Synopsys