Synopsys Technology Symposium 2022 - Oulu

Synopsys is hosting a Technical Symposium to provide an opportunity for users to stay connected with the latest Implementation, Verification and Analog/RF Design tools and roadmaps.

 

The event is organized in three parallel tracks for the topic of your interest including Synopsys Keysight Analog/RF Design, Digital Implementation and Digital Verification.

Event Information


Synopsys Technology Symposium - Oulu

 

Wednesday, 5 October

9:00 a.m. – 12:00 p.m.


Technopolis Sepänkatu 20,
Ydinkeskusta 90100 Oulu

Agenda


09.00 a.m.

Coffee and Registration


09.15 a.m.

Session 1


10:30 a.m.

Break


10.45 a.m.

Session 2


12:00 p.m.

Lunch

09.00 a.m.

Coffee and Registration


09.15 a.m.

Session 1


10:30 a.m.

Break


10.45 a.m.

Session 2


12:00 a.m.

Lunch

09.00 a.m.

Coffee and Registration


09.15 a.m.

Session 1


10:30 a.m.

Break


10.45 a.m.

Session 2


12:00 a.m.

Lunch

Track Details


Analog and RFIC Design using Synopsys and Keysight Integrated Solution – Analog/RF design Track

Front-to-back IC design and verification of designs spanning the frequency range of sub-6GHz to millimeter waves using Synopsys Custom Design Family, with integration of Keysight Pathwave RFIC Design (GoldenGate) for RF simulation and Pathwave RFPro for electromagnetic (EM) analysis. The session is joined by CoreHW, leading fabless semiconductor company providing design services, intellectual property (IP) and semiconductor solutions, to present their experiences with the flow.


Digital Implementation Track

This track will cover the technologies for high-end RTL to GDSII design in latest process nodes. The session captures an overview of newest solutions such DesignDash for big data analytics driven design, Synopsys award winning DSO.ai, 3DIC and Silicon Lifecycle Management followed by tooling updates from synthesis to Place&Route to power optimization/analysis and signoff.


Digital Verification Track

This track will cover the latest technologies to help reach coverage closure fast. The session will cover innovations in ML/AI enabled digital verification and design debug to make regressions more efficient and eliminate errors. We explore the full integrated verification solution continuum from tools for finding bugs even as code is being written, to simulation, debug, static, and formal for uncovering hard-to-reach corner case bugs.

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