Cloud native EDA tools & pre-optimized hardware platforms
Synopsys is hosting a Technical Symposium focusing on critical aspects of doing state of the art designs at established and emerging nodes. This event provides an opportunity for users to stay connected with the latest innovations as well as getting tips & tricks and best practices that fellow users and Synopsys experts will share.
Multiple tracks will be offered including Cloud, Low-Power, Functional Safety, Digital Implementation and Verification, Test, Signoff, and Custom & Analog Mixed-Signal, where experts will update you on exciting new technologies and features.
We will conclude the day with a social event where you will have the opportunity to meet and discuss with your industry peers and Synopsys experts in an informal atmosphere while enjoying some refreshments.
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Tuesday, 11 October
9:00 a.m. – 6:00 p.m.
World Trade Center, 5-7, Place Robert Schuman, 38000 Grenoble
The event will start with Registration and Breakfast from 9:00 a.m. to 10:00 am.
Alessandra Costa, Senior Vice President, Customer Success Group, Synopsys (Auditorium)
Every few hundred years a renaissance of innovation occurs. The past can often be used to predict the future. Alessandra will examine some of the historical aspects of innovation renaissance. She will then look at current market forces that are re-shaping the innovation model to illuminate the current renaissance we are experiencing.
Manufacturing complexities 5nm and below are driving the need for a faster, convergent and high productivity physical verification solution. IC Validator continues to deliver innovations in scalable performance, high productivity and robust debugging. In this presentation, learn about latest IC Validator technology for physical verification productivity and performance and how to use these technologies in your design flow.
Fully integrated in StarRC extraction engine, Virtual Metal Fill (VMF) estimates the metal fill impact on parasitics and timing without the actual fill insertion process.
Avoiding the timing-consuming process of metal fill during each ECO loop promises game changing TAT reduction.
The benefits of this feature go actually beyond:
• Actual extraction step is quicker,
• Excellent correlation of VMF and RMF prevents QoR degradation from metal fill insertion
• Less data overhead, since no fill data needs to be manipulated.
During this presentation, we will share some success stories from customers who have reported some major productivity gains after having set up this flow.
Timing closure traditionally uses a fixed margin for IR-Drop, based on a targeted max IRDrop estimation. This leads to over-design on a majority of the paths, but can also lead to silicon failures when targeted IR-Drop is under-estimated. As a matter of fact, IR-Drop reduction during implementation, as well as IR-Drop aware STA helps to reduce over-design and TAT. In this presentation, we will cover Synopsys Rail integrity flow to reduce IR-Drop impact on designs.
As we shift left in the ASIC Flow, Synopsys TestMAX Family of DFT products provides a comprehensive integration flow from RTL to ATE. TestMAX Manager provides a Tcl based framework for the interoperability of these products, enabling flow automation and customization along with design introspection and editing capability. This presentation will give an overview of these DFT Solutions with special emphasis on TestMAX Access and its support for IEEE 1687.
TestMAX Manager supports multiple features and technologies. Each feature, each technology also has various options. Designs usually have several hierarchical levels, requiring DFT features for integration. This flexibility leads to nearly infinite combinations of a Design for Test (DFT) implementation.
The TestMAX Mainstream and Automotive flows guide the users through a proven path of the DFT implementation thanks to a documented and validated example testcase and exercise the interoperability between TestMAX Manager and the other tools involved in the design development. This presentation is intended to give necessary information on the DFT flow, the example design and the exercised features and technologies.
SoC designs Low Power intents are described by UPF files. Digital verification flows are taking advantage of this description to anticipate as much as possible potential functional power issues during operating modes. Mixed signal environments are based on digital verification environments. The usage of same Low Power description is possible and connection is done between analog supplies and UPF.
One of the aims of mixed signal verifications is to verify power modes transitions that could not be represented and simulated in a digital way. In this paper we will show the penalty that Low Power verbosity introduced with VCS-AMS usage. We will propose a simple solution, using UPF API described in “IEEE Standard for Design and Verification of Low-Power".
This session will present the recent new features of VCS Primesim including the new Real Time Switching View (RTSV) feature to balance between accuracy and performance of the simulation, the support of Monte Carlo and Sigma Amplification in Mixed Signal Simulation.
NextGen SoCs with advanced graphics, computing, machine learning and artificial intelligence capabilities are posing new unseen challenges in verification signoff. It is important to reduce turnaround times and enable faster time-to-market. Emulation helps verify software scenarios and longer running validation tests which cannot be run in a simulation environment. The need of the hour is a fast emulator with full debug capabilities and also ensuring a high throughput. The Synopsys ZeBu emulator is the industry fastest emulator which ensures a “shift-left” in overall emulation signoff and at the same time ensures that no subtle bugs escape into silicon.
With increasing SoC complexity, growing design sizes and advanced graphics and computing architectures, early and efficient verification signoff is important to reduce turnaround times and enable faster time-to-market. Emulation platforms play a significant part in running long tests and verifying real world scenarios. A fast emulator with full debug capabilities is needed to achieve this. This paper will cover the details on the evaluation done for one of the designs at NXP using Synopsys ZeBu EP1, and discuss how it helped to achieve performance goals.
The performance of the development platform has become more important than ever with the growing complexity and amount of software stacks. HAPS offers the industry's highest performance and most scalable prototyping system. It delivers the next innovation in prototyping with the fastest performance, highest debug productivity and enterprise scalability to accelerate software development, system validation and verification.
During this presentation, you will learn how HAPS automates prototyping and at-speed HW/SW debug. Kalray will share their experience on HAPS-100 for the verification of their Massively Parallel Processor Array SoC.
Cloud is everywhere – for chip design, companies large, medium, and small are evaluating their options in using high-performance computing (HPC) infrastructure to accelerate and differentiate their designs. In this session, we will discuss the drivers and challenges of moving EDA workloads to the cloud and how leading design teams are maximizing the benefits of moving to the cloud.
In the two years since introduction, Synopsys’ DSO.ai™ has enjoyed rapid adoption around the globe and across varying market segments. With growing usage on real-world designs, customers have applied the power of DSO.ai and its learning system to optimize varying aspects of the chip design workflow. In this session, Synopsys experts will showcase the library of design-space applications (aka “SpaceWare apps”) deployed by customers, highlighting those that are readily available to jump-start key design tasks and unique apps that have been built using the customizable environment in DSO.ai.
The Implementation of CPU cores at advanced design nodes (N7) usually requires lots of efforts and multiple iterations to achieve the level of performance needed for the product. Multiple key metrics needs to be achieved for competitiveness and requires significant efforts to improve performance efficiency but still to preserve acceptable productivity.
To improve PPA targets by exploring a huge design search in a minimum of time, DSO.ai technology brings both massive AI and Cloud infrastructure as a center point of the design activity. This presentation will share an experience using both DSO.ai and Cloud infrastructure on a high-speed ARM core.
Current derating solutions applied to deal with increased design variability at advanced nodes and low power designs, introduce over-margining and timing pessimism impacting PPA directly.
PrimeShield introduces new solutions in place of the current derating approaches, to reduce the pessimism and improve design robustness through:
• Analyzing and improving design variation robustness, including global and local effects
• Analyzing design at High sigma using Fast Monte Carlo and Machine Learning
• Improving voltage robustness and I/R drop resilience, while reducing Vdd or increasing frequency
• Analyzing global skew, including Vt skew, Device skew or Interconnect skew, allowing to remove margin and/or reducing number of scenarios.
This presentation will cover how PrimeShield can help improving the robustness and performance by tackling the over margining, through the solutions above.
Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. In this tutorial, we will cover a full-flow voltage optimization and closure methodology to achieve the best performance-per-watt results for the most demanding semiconductor segments.
Modeling circuit performance degradation due to transistor aging has a been a long-standing challenge in STA. Highly sensitive to stress condition and signal activity, the aging effect can vary significantly due to different operating conditions. It is extremely expensive to account for all possible aging conditions during cell characterization. As a result, aging effect has been treated with derate-based methodology, which often becomes overly pessimistic or lacks signoff coverage.
This presentation will showcase an innovative solution that delivers high signoff accuracy to avoid pessimism related to derate-based solution. Combining advanced delay modeling techniques with machine learning, the novel approach is capable of performing accurate scaling across a wide range of aging conditions with low runtime overhead. The presentation will also demonstrate a fully-automated flow that performs path-level aging HSPICE simulations for rigorous accuracy validation.
The emerging paradigm shift towards Silicon Lifecycle Management is changing the way the Semiconductor Test and SoC communities think about device and system performance, silicon health and predictability. The new era of SLM has opened up opportunities for developing new, insightful monitoring and analytics technologies that are now providing solutions to the optimization challenges faced by test teams, chip and system developers across a wide range of applications. Silicon Lifecycle Management is one of the most exciting areas of evolution for the semiconductor industry and based on the value it brings to each phase of the device lifecycle from early design right through to in-field.
As Silicon Lifecycle Management continues to gain momentum it is just a matter of time before adopting and using SLM is standard procedure on every project. The Synopsys Silicon Lifecycle Management family has been developed to improve silicon operational metrics at every phase of the device lifecycle and has been built on a foundation of enriched in-chip observability, analytics and integrated automation. Embedded monitors enable deep insights from silicon to system. Meaningful data is gathered at every opportunity for continuous analysis and actionable feedback.
Today Silicon Lifecycle Management (SLM) is generating a lot of interest within the semiconductor test and SoC communities as it will soon allow designers to optimize and track their devices throughout their entire lifetimes, from the early design phase, through manufacturing and finally during in-field operation. To aid in this new process, added visibility within the device is required and provided by the use of embedded monitors to gather key environmental and structural data from the device. This critical data is then and transported off-chip to a unified SLM database ready for analysis.
Targeted analytics opportunities therefore lie within each of the lifecycle phases. In the design phase, silicon parametric data can be fed back for better power and performance design tuning. During the ramp phase, precise assessments can be made to quickly identify systematic issues to speed up yield ramp. The production phase utilizes analytics to greatly improve device screening for increased quality and reliability as well as reduced test cost while maintaining high yield. The final in field phase is where the collection and analysis of in-chip monitor data can help monitor the health and performance of the device, allowing for predictive maintenance and performance tuning when allowed to enable device longevity and prevent any disruptive downtime in the overall system hosting the device.
In this presentation, we will look at how Synopsys is starting to implement a holistic analytics solution as part of its integrated SLM family - complete end-to-end integrated analysis across the life of the device. In-silicon health, observability and insight are key when it comes to SLM and as an industry we can no longer afford to ignore what is happening inside our devices throughout their lifetime
The Synopsys integrated Silicon Lifecycle Management (SLM) family is built on a foundation of enriched on-chip observability, high speed data access and analytics.
Embedded in-chip environmental and structural monitors enable this enhanced visibility and ensure optimal silicon health is achieved throughout the device lifecycle. In-chip PVT monitors provide real time data on dynamic conditions like process variability, voltage supply and thermal activity and Path Margin Monitors measure the timing margins of real functional paths. The meaningful data from these types of embedded SLM monitors is gathered at every at every stage of the silicon lifecycle. The data is then transported off-chip where analytics is applied allowing insightful decisions to be made and action to be taken.
Reliability verification for today's hyper convergent designs needs EDA tools to offer a holistic approach that spans throughout the lifecycle of the chip addressing various aspects of reliability from device and electrical overstress, fault tolerance, ESD, design variations, power integrity, device aging and ElectroMigration. Synopsys PrimeSim Reliability Analysis provides a comprehensive unified workflow of proven analysis solutions that provides a fast and accurate way to achieve reliability compliance. In this session we will review the key features of PrimeSim Reliability and PrimeWave Design Environment and how users can benefit from it to perform a comprehensive reliability verification.
STMicroelectronics and Synopsys have been collaborating in the past years to increase large memory designs validation coverage for latest processes (40nm, 28nm and 18nm technologies) with optimized simulation runtimes using Monte-Carlo statistical method and advanced analysis for high sigma values.
PrimeSim XA Advanced Variability Analysis (AVA), Sigma Amplification Selective Variation (SA) and Block Specific Sigma Amplification (BSSA) applications have been used to respectively set a sigma value for a selected part of the design, and to set different amplification factors to different circuit blocks.
These applications demonstrated a real benefit for memory validation in the real context for design, evaluation and reliability analysis phases and for memory failure analysis, which cannot be done with traditional Monte-Carlo methodology.
This presentation introduces the verification challenges around constrained random verification. It provides an overview of VCS Intelligent Coverage Optimization (ICO) which is designed to be used during all stages of testbench development, to gain expose more bugs, improve non-regression Turnaround time and provide testbench insights which in turn help write better constraints that are conducive to faster coverage convergence. VC Execution Manager, which automates coverage-driven verification execution, has been enhanced to integrate with ICO and we present here the integrated workflow and results.
Efficiency is crucial when working with SystemVerilog RTL design and UVM Testbenches. Syntax mistakes, coding violations, and the resulting problems increase the daily stress of engineers. Synopsys Euclide solves many of these problems by providing seamless incremental code and lint checking during SystemVerilog code bring up for both design and testbench while providing valuable feedback, seamless code navigation and a powerful autocomplete capability.
Attend this session to discover several new Euclide features that are helpful when working with new workflows. This talk will also share ideas on how to structure your Euclide setup to get the best performance, tuned to the varying team requirements.
Certitude’s mutation-based approach and VC Formal FTA app assess verification effectiveness for simulation and formal environments by measuring the environment’s ability to activate, propagate and detect potential bugs.
This presentation describes innovative approaches to qualify mixed verification environments (formal, simulation) and high configurable IPs. It will cover the following topics :
• How to get combined coverage for mixed verification environments and high configurable IPs
• How to speed up Certitude functional qualification for simulation flow by importing FTA results from formal environment in the context of mixed verification environment.
• And finally, how to improve the Certitude detection performance by using the “Dump Replay” feature.
Energy efficiency is critical in all major application segments. This session will cover a holistic approach to addressing power consumption in SoCs starting from architecture to RTL to implementation and signoff. A key aspect of the solution is how power-critical vectors derived from software workloads drive power analysis, exploration and optimization at each stage of the design flow to maximize power savings based on actual application scenarios.
PrimePower RTL power estimation leverages the Predictive Engine from Synopsys' RTL Architect™ product to provide RTL designers with fast, scalable, and accurate power estimation for early analysis of RTL blocks, subsystems, and full-SoCs. PrimePower RTL enables designers to analyze, explore, and optimize their RTL with confidence, improving power, energy efficiency, and shortening the design cycle.
In this tutorial, we will cover how designers can perform PPA analysis early in the design cycle with 3X faster productivity. Built on the unified Fusion Data Model, RTL Architect provides fast physical aware feedback leveraging Synopsys' world-class implementation and golden signoff solutions to deliver results that correlate-by-construction.
During a late-stage Functional ECO situation, the need is to implement rapidly while ensuring that the functionality and timing requirements are met without any sacrifice to the synthesis QoR.
To achieve maximal quality of results (QoR) in synthesis, designers leverage techniques such as retiming, multibit banking, and advanced datapath optimizations, which are part of the Synopsys synthesis solutions. However, the automated ECO tool needs to be sophisticated enough to generate optimal patches in the presence of such aggressive optimizations.
Synopsys Formality ECO is a revolutionary new approach which leverages both the Equivalence Checking technology and in-house compilation technologies from either the Design Compiler or Fusion Compiler solutions. Formality ECO starts the generation process as soon as the ECO RTL is ready. This gives the designer a head start and saves precious time during late-stage ECOs by avoiding a full ECO synthesis. This approach helps isolate the minimal set of ECO regions required to capture the change in the ECO RTL and then performs a “targeted synthesis,” which is an ECO-aware smart compile that synthesizes only the regions of change. This synthesis supports all the optimizations needed, eliminating any compromise in the QoR.
Formality ECO technology has demonstrated the ability to deliver up to 10x faster TAT, up to 5x smaller patches, and support in achieving maximal QoR for designs in a wide range of application areas. In this seminar, learn about Formality ECO: a revolutionary way of doing functional ECOs.
While facing challenges with designs getting larger and costing time to be signed off by STA tools on time with same resources, Synopsys signoff tools are offering a methodology to achieve better performance with similar quality of results. To do that, HyperScale and HyperGrid technologies are two signoff flows performing hierarchical and partitioning analysis using PrimeTime core flow and engine. The purpose of this presentation is to share technical details on how large designs can be signed off using these two technologies.
When you’re developing a multi-million-gate chip, every seemingly small bit of power and area you can save from every block multiplies into a big impact on the overall power-performance-area (PPA) equation. An ECO (engineering change order) file is issued to the physical implementation (layout) tools to make final tweaks and correct any issues found. This process worked well for designs at older technology nodes, but it has become a big challenge in electronic design signoff at the advanced technology process nodes. This challenge frequently takes numerous iterations to converge, consumes growing hardware resources, and removes predictability in project schedules. This process has become worse in recent years. It is common for the ECO process to consume 50% or more of the design-closure time at advanced technology nodes.
Design teams are constantly in need of new technologies to minimize test time and test data volume, accelerate design-for-test (DFT) development, and ensure optimal design implementation. In this tutorial, we will provide guidance on using two key TestMAX technologies that address these challenges: DFTMAX SEQ codec which encompasses flexible sequential compression to significantly reduce test data volume for large designs; and Streaming Fabric which is a high-throughput bus-based data delivery structure designed to reduce test time while easing its physical implementation. In addition, key runtime improvements for ATPG will also be covered.
As designs are growing and GPIO availability for scan is reducing, it has become imperative to use functional I/Os for scan-testing. This presentation will give an overview of how adaptive high bandwidth testing can be done over functional interface.
STMicroelectronics designs complex Systems on a Chip (SoC) in advanced technology nodes for market segments such as enterprise, networking, MCU and high reliability automotive. These products are designed with thousands of memory instances with very high-quality standards. The production goals are to accelerate cycle time in the New Product Introduction (NPI) phase and shorten turn-around-time in failure analysis when defective parts with embedded memories are detected.
Synopsys STAR Memory System is used to test, repair and diagnose embedded memories while Synopsys Yield Explorer performs analytics on memory diagnostic data to help quickly identify and resolve systematic failure mechanisms for the most advanced process nodes.
As defect simulation becomes mainstream to cater to stringent safety and DPPM requirements of analog / mixed-signal ICs, there is a need to enable designers, safety experts, and test engineers with modern tools and utilities to help drive down the overall defect campaign throughput and cost while simultaneously allowing them to scale from block-level to sub-system level analysis.
This session provides an overview of the new defect analysis app in PrimeWave Reliability Environment and an update on new utilities in PrimeSim Custom Fault that together help improve analog test coverage and overall defect campaign throughput and productivity.
In modern electronic designs, more and more memories are embedded in a single chip. With the latest technologies, defects due to the manufacturing process are more prone to occur in the periphery of the memory. Obtaining a fast and accurate localization of such defects has become much more difficult with traditional diagnosis approaches that do not allow a fast-enough yield learning and improvement.
To address this issue, STMicroelectronics have developed a new diagnosis flow for SRAMs aimed at determining the localization of any given defect and thus, to precisely guide the Failure Analysis phase.
This presentation will describe the advanced memory diagnosis introduced before the failure analysis stage to enhance diagnosis precision and runtime based on the following Synopsys products:
• PrimeSim XA to extract each potential fault on the active nets from the electrical and topological fault signatures obtained through traditional methods.
• StarRC to extract physical information (open contact and open via) on these active nets identified by PrimeSim XA.
• PrimeSim CustomFault to inject automatically all open/short mos terminals, net to net bridges, open contacts and open vias.
Each result is automatically compared to the silicon golden results to identify the real defect candidates. Results presenting a failing IO on a Single Port 4096x32 SRAM memory design will be shared to backup this new flow.
Fault diagnosis in electronic circuits is a key process to ensure the safety of devices in critical applications such as automotive. Concerning analog circuits in some case this is a long and difficult step to perform without simulation tools and any automation. For this reason, we introduced CustomFault to create a simulation-based fault diagnosis flow and automate this process for analog circuits.
This presentation describes the use of CustomFault in combination with Avalon to facilitate and speed up the fault diagnosis process inspired by the approach used for digital circuits (TetraMax).
Specifying the low power (LP) intent of design in the UPF file is a manual, tedious process and does not always scale from one abstraction level to another or from one tool to another in the SoC design flow. Built on the Synopsys Verdi advanced debug platform, Verdi UPF Architect provides an automated flow to create and optimize the UPF from IP to SoC. Verdi UPF Architect facilitates a single golden power intent allowing the designer to generate UPF, meeting various tool requirements in the flow. Also learn how the generated UPF can be further optimized using the Synopsys VC LP static low power verification solution.
Current ICs (Integrated Circuits) include million gates IPs (Intellectual Properties) interfacing to each other through multiple asynchronous clock domains. As a consequence, to ensure the correctness of the asynchronous communications, exhaustive CDC (Clock Domain Crossing) structural checks must be performed. They require all clocks to be concurrently propagated. In this paper, we will present the different steps required to manage the constraints generation and elaboration during CDC and RDC analysis. An efficient static low-power verification approach concerning low-power components defined through the UPF file directives will also be illustrated. Lastly, we will conclude by demonstrating ways to manage the different aspects of constraints using VC SpyGlass as an open Tcl tool allowing the elaboration of additional and custom features increasing the Quality of Results (QoR) compared to the native platform.
As of today, wrongly implemented Clock Domain Crossing (CDC) are well known to cause real design issues. Lot of efforts are done to be able to detect them all on ASIC. But a less know type of crossing, Reset Domain Crossing (RDC), can be equally catastrophic. Nowadays, the number of resets on design is constantly growing. For power management reason, it’s not rare to have hundreds of different resets. The purpose of this presentation is to explain the different aspect of the RDC issues, how to detect them all and how to manage them to ensure a clean robust RDC analysis closure.
The Failure modes of each component in the design and the distribution of component failure mode on the product functionality are measured by the Failure Mode Distribution (FMD) of those failures.
The FMD is entered as an estimation value in FMEDA is deemed acceptable for ASIL A/B. But, ISO26262 requires a quantified analysis of FMD for traceability especally for ASIL D. There are several approaches in presenting the FMD data, based on a qualitative pin distribution analysis up to quantitative analysis. This presentation shows an automated tool-based flow and introduces the quantitative FMD calculation and reporting through TestMAX FuSa tool.
An example will be presented by Synopsys Solution Group detailing how TestMAX FuSa is used in the functional safety development flow and the quality of the reported results compared to other approaches. FMD is an important input to the FMEDA of ARC Processor cores. Usage of an advanced methodology through quantitative analysis gives higher accuracy in results during the safety analysis. This also allows to arrive at a more precise estimation of SPFM metric for a combination of different safety mechanisms including software-based self-test running in ARC processor core.
During this session, we will review the impact of Functional Safety on verification and implementation.
We present an approach which limits the typical negative schedule and resources impact, without compromising on safety or even improve compared to traditional approach.
11:00 - 11:15 (Atrium)
12:15 - 13:30 (Atrium)
15:00 - 15:30 (Atrium)
17:00 - 18:00 (Atrium)