Synopsys Technology Symposium Barcelona

Synopsys and AESEMI (Asociación Española de la Industria de Semiconductores) are hosting a Technical Symposium to provide an opportunity for users to stay connected with the latest Implementation, Verification and Analog/RF Design tools and roadmaps. The event is organized with separate sessions for Synopsys Keysight Analog/RF Design and Digital Design.

Registration Synopsys Technology Symposium 2022 - Barcelona

Event Information


Synopsys Technology Symposium 2022 - Barcelona

 

Thursday, 20 October

10:00 a.m. – 1:30 p.m.

Hotel NH Sants Barcelona, Numancia, 74, 08029 Barcelona

Agenda


10:00 a.m. – 10:15 a.m.

Coffee and Registration

10:15 a.m. - 10:30 a.m.

AESEMI: Spanish Semiconductor, Present and Future

10:30 a.m. – 11:30 a.m.

Analog and RFIC Design using Synopsys and Keysight Integrated Solution

11:30 a.m. – 11:45 a.m.

: IMASENIC Designing CMOS sensor with Synopsys AMS flow

11:45 a.m. - 12:15 p.m.

Break

12:15 p.m. - 13:30 p.m.

Digital Design

13:30 p.m.

Lunch Break

Track Details


Analog and RFIC Design using Synopsys and Keysight Integrated Solution –The Analog/RF design session covers front-to-back IC design and verification using Synopsys Custom Design Family. Custom Design product family accelerates the development of robust analog & mixed-signal design and RF designs spanning the frequency range of sub-6GHz to millimeter waves using Synopsys Custom Design Family, with integration of Keysight Pathwave RFIC Design (GoldenGate) for RF simulation and Pathwave RFPro for electromagnetic (EM) analysis. The session is joined by CoreHW, leading fabless semiconductor company providing design services, intellectual property (IP) and semiconductor solutions and Imasenic developer of state-of-the-art custom CMOS image sensors to present their experiences with the flow.

 

Digital Design session will cover the Synopsys solution from comprehensive IP portfolio to high-end RTL to GDSII design and advanced verification - in emerging and established process nodes and various application domains such as automotive, high-performance computing and IoT. The session captures an overview of newest implementation and verification solutions such Synopsys award winning DSO.ai to autonomously explore the chip design solution space, RTL Architect to reduce development cycle and improve QoR, DesignDash for big data analytics driven design, 3DIC, Silicon Lifecycle Management and ML/AI enabled digital verification and design debug.