Synopsys are hosting a Technical Symposium to provide an opportunity for users to stay connected with the latest Implementation, Verification and Analog/RF Design tools and roadmaps. The event is organized with 2 sessions: Synopsys Keysight Analog/RF Design and Digital Design.
Spaces are limited so please register now!
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Synopsys Technology Symposium - Athens
Synopsys Technology Symposium 2022 - Athens
Thursday, 24 November 2022
09:30 a.m. – 12:30 p.m. UTC +2
President Hotel, 43 kifissias Av. | Athens, Greece, 115 23
Registration starts at 9:30 a.m. and conclude at 12:30p.m. followed by lunch.
Coffee and Registration
Analog and RFIC Design using Synopsys and Keysight Integrated Solution
Analog and RFIC Design using Synopsys and Keysight Integrated Solution –The Analog/RF design session covers front-to-back IC design and verification using Synopsys Custom Design Family. Custom Design product family accelerates the development of robust analog & mixed-signal design and RF designs spanning the frequency range of sub-6GHz to millimeter waves using Synopsys Custom Design Family, with integration of Keysight Pathwave RFIC Design (GoldenGate) for RF simulation and Pathwave RFPro for electromagnetic (EM) analysis. The session is joined by ThessIC, a leading ASIC fabless design company developing its own IoT and automotive MCU ICs and offering services for low cost, low power and fully customizable solutions.
Digital Design session will cover the Synopsys solution from comprehensive IP portfolio to high-end RTL to GDSII design and advanced verification - in emerging and established process nodes and various application domains such as automotive, high-performance computing and IoT. The session captures an overview of newest implementation and verification solutions such Synopsys award winning DSO.ai to autonomously explore the chip design solution space, RTL Architect to reduce development cycle and improve QoR, DesignDash for big data analytics driven design, 3DIC, Silicon Lifecycle Management and ML/AI enabled digital verification and design debug.