Memory Technology Symposium

Join this Virtual Event

Advancements in memory technology are fueling rapid growth in big data applications across AI, 5G, Automotive, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated, while the latest technology nodes have introduced some new ones. At Synopsys, there is a corporate-wide commitment to developing broad-based solutions that address these challenges.

 

Why Attend?

The Synopsys Memory Technology Symposium, a first-of-its-kind virtual event dedicated to memory design and development, aims to provide a forum for leading Memory, IP, SoC Companies and Synopsys experts to share their perspectives on the industry’s most compelling and topical challenges across four themes: Design Technology Co-optimization (DTCO), Design Shift Left, IP, and Silicon Reliability. Register to learn more!​

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Presenting Companies


Agenda At-a-Glance

Learn more about the themes we will explore during this virtual event. More information around sessions are being confirmed daily, so be sure to check back often for new information.

Tue. November 29, 2022
08:00 - 08:25 AM PST
Synopsys Keynote​: New Paradigm in Semiconductor Design
  • Antonio Varas, Chief Strategy Officer, Synopsys
Design Technology Co-optimization (DTCO)
Tue. November 29, 2022
08:25 - 08:45 AM PST
Flat Field Transistor (FFT) DTCO Optimization for DRAM Applications
  • Asen Asenov, CEO of Semiwise and Professor at The University of Glasgow
Design Technology Co-optimization (DTCO)
Tue. November 29, 2022
08:45 - 09:10 AM PST
Memory DTCO: A Variability Perspective
  • Salvatore Amoroso, R&D Engineer, Synopsys
Memory Design Shift Left & Digitization
Tue. November 29, 2022
09:10 - 09:25 AM PST
Innovatory Timing Margin Simulation w/ Power SPF using PrimeSim Pro
  • Tae-Jun Lee, Technical Lead, SK hynix
Memory Design Shift Left & Digitization
Tue. November 29, 2022
09:25 - 09:45 AM PST
Static Timing Analysis of Embedded Memories: a customer’s perspective
  • John Barth, Sr. Member, Technical Staff, Synopsys
IP Solutions
Tue. November 29, 2022
10:00 - 10:15 AM PST
SiMa.ai's MLSoC™ with LPDDR4
  • Srivi Dhruvanarayan, VP of Hardware Engineering, SiMa.ai
IP Solutions
Tue. November 29, 2022
10:15 - 10:35 AM PST
Achieving High Performance From the Memory System of an Arm Server SoC
  • Emad Khan, Staff Engineer, Arm
Silicon Reliability
Tue. November 29, 2022
10:35 - 10:55 AM PST
Statistically Aware and Aging-Resilient Design of SRAM
  • Kedar Janardan Dhori, Principal Engineer, STMicroelectronics
Silicon Reliability
Tue. November 29, 2022
10:55 - 11:15 AM PST
Silicon Lifecycle Management for Emerging Memories
  • Yervant Zorian, Synopsys Fellow
Industry Panel
Tue. November 29, 2022
11:15 - 12:05 PM PST
Panel: Need for New Paradigms in Memory Design and Development 
  • Huijuan Wang, Sr. Director Physical Design, Western Digital
  • Il Park, VP of Advancement Solutions, SK hynix
  • Sandeep Bhatia, DFx Lead, Google
  • Victor Moroz, Synopsys Fellow
APAC + -
Wed. November 30, 2022
08:00 - 08:25 AM CST
Synopsys Keynote​: New Paradigm in Semiconductor Design
  • Antonio Varas, Chief Strategy Officer, Synopsys
Design Technology Co-optimization (DTCO)
Wed. November 30, 2022
08:25 - 08:45 AM CST
Flat Field Transistor (FFT) DTCO Optimization for DRAM Applications
  • Asen Asenov, CEO of Semiwise and Professor at The University of Glasgow
Design Technology Co-optimization (DTCO)
Wed. November 30, 2022
08:45 - 09:10 AM CST
Memory DTCO: A Variability Perspective
  • Salvatore Amoroso, R&D Engineer, Synopsys
Memory Design Shift Left & Digitization
Wed. November 30, 2022
09:10 - 09:25 AM CST
Innovatory Timing Margin Simulation w/ Power SPF using PrimeSim Pro
  • Tae-Jun Lee, Technical Lead, SK hynix
Memory Design Shift Left & Digitization
Wed. November 30, 2022
09:25 - 09:45 AM CST
Static Timing Analysis of Embedded Memories: a customer’s perspective
  • John Barth, Sr. Member, Technical Staff, Synopsys
IP Solutions
Wed. November 30, 2022
10:00 - 10:15 AM CST
SiMa.ai's MLSoC™ with LPDDR4
  • Srivi Dhruvanarayan, VP of Hardware Engineering, SiMa.ai
IP Solutions
Wed. November 30, 2022
10:15 - 10:35 AM CST
Achieving High Performance From the Memory System of an Arm Server SoC
  • Emad Khan , Staff Engineer, Arm
Silicon Reliability
Wed. November 30, 2022
10:35 - 10:55 AM CST
Statistically Aware and Aging-Resilient Design of SRAM
  • Kedar Janardan Dhori, Principal Engineer, STMicroelectronics
Silicon Reliability
Wed. November 30, 2022
10:55 - 11:15 AM CST
Silicon Lifecycle Management for Emerging Memories
  • Yervant Zorian, Synopsys Fellow
Industry Panel
Wed. November 30, 2022
11:15 - 12:05 PM CST
Panel: Need for New Paradigms in Memory Design and Development 
  • Huijuan Wang, Sr. Director Physical Design, Western Digital
  • Il Park, VP of Advancement Solutions, SK hynix
  • Sandeep Bhatia, DFx Lead, Google
  • Victor Moroz, Synopsys Fellow

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