Synopsys and Infineon are hosting a two-day Symposium live and in-person at Am Campeon. This event will be held on 28th and 29th June 2023: Session will also be accessible via Webex.

The Symposium promises to be an informative and productive event running across four tracks:

Track One

Implementation and Signoff


Track Two

Verification


Track Three

AMS and Technology Development


Track Four

IP and Silicon Lifecycle Management


We look forward to sharing information about new and exciting EDA, IP and FuSa Technologies from Synopsys.

Places are limited so please sign up now.

Register Today

Track Information


Track 1 - Implementation and Signoff
28.6.2023 9:00-16:15

Session Details:  Learn about the technologies that enable shift left in design methodology, delivering maximum PPA entitlement and significant productivity benefits across the entire RTL-to-signoff flow.


Track 2 - Verification
28.6.2023 9:00-16:15

Session Details:  Achieve fastest turnaround time with industry leading verification, debug, RTL static signoff, Low Power technologies, and silicon-proven Verification IP. The fastest emulation system on the market for earlier software bring-up, and validation of the entire system with Virtual prototyping and Platform Architect.


Track 3 - Analog/Mixed Signal Design
& Technology Development
29.06.2023 9:00-16:15

Session Details: State of the art Custom Design Family is a unified suite of design and verification tools that accelerates the development of robust analog and mixed-signal designs. The family features Custom Compiler™, a fast, easy-to-use design, and layout solution, PrimeSim™ solution which delivers industry-leading circuit simulation performance, and best-in-class technologies for parasitic extraction, reliability analysis, and physical verification.

This track also provides an overview of the Synopsys roadmap and development directions for Sentaurus TCAD, QuantumATK, TCAD-to-SPICE and Power DTCO solutions.  Early Process Development, Advanced Lithography and Yield Management to optimize tradeoffs between speed, area, power, test, and yield. 

SLM Production and Process Analytics is a unique analytics solution spanning design and product manufacturing phases as part of the Synopsys Silicon Lifecycle Management (SLM) family.  The solution automatically highlights silicon data outliers, enabling engineering teams to quickly identify and correct underlying issues in the semiconductor supply chain.


Track 4 - IP & Silicon Lifecycle management
29.06.2023 9:00-16:15

Session Details: High-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems.CoreTools session will provide overview methodology to enable IP reuse.

Integrated Silicon Lifecycle Management (SLM) family of products improves silicon health and operational metrics at every phase of the device lifecycle. Synopsys SLM family of products is built on a foundation of enriched in-chip observability, analytics and integrated automation. Monitors enable deep insights from silicon to system. Meaningful data is gathered at every opportunity for continuous analysis and actionable feedback.  


Closing Session and Networking reception
28.06.2023 16:15-17:30
29.06.2023 16:15-17:30

Session Details: Closing statements and Networking reception with Infineon and Synopsys colleagues

Agenda


8:30-8:50

Breakfast


CS736389942-China Dev Con.
09:00-09:45

Synopsys Keynote

Sassine Ghazi, President & COO, Synopsys


09:45-10: 00

Break

10:00 - 10:45 AM CET
Designing next generation SoCs with Fusion Platform
  • Arvind Narayanan
10:45 - 11:30 AM CET
Synopsys FuSa  Solutions
  • Alessandra Nardi

11:30-12:30

Lunch

12:30 - 01:15 PM CET
How AI is driving the next wave of Innovation in EDA
  • Arvind Narayanan
01:15 - 02:00 PM CET
RTL Architect Design Platform for a convergent design flow
  • Arvind Narayanan
02:00 - 02:45 PM CET
Innovations for Today’s STA Trends and Signoff Robustness/Variation Analysis
  • Manoj Chacko

14:45-15:00

Break

03:00 - 03:45 PM CET
Advanced Node Extraction and Physical verification for faster TAT with StarRC and ICV
  • William Ruby
03:45 - 04:30 PM CET
PrimeClosure, Golden Signoff ECO
  • Manoj Chacko
10:00 - 10:45 AM CET
The Era of Autonomous Verification
  • Bradley Geden
10:45 - 11:30 AM CET
Verdi Debug Innovations & Autonomous Debug
  • Bradley Geden

11:30-12:30

Lunch

12:30 - 01:15 PM CET
Low Power Verification & Management with UPF Architect and VC LP Technologies
  • Bradley Geden
01:15 - 02:00 PM CET
Comprehensive Static Verification Platform with VC SpyGlass : CDC, RDC, Constraints, Glitch and Lint
  • Bradley Geden
02:00 - 02:45 PM CET
Shift-Left with VC Formal and Formal Verification
  • Bradley Geden

14:45-15:00

Break

03:00 - 03:45 PM CET
Accelerating Key Use cases with Hardware Assisted Verification
  • Samskrut Konduru
03:45 - 04:30 PM CET
Synopsys Energy Efficiency Solution: from Architecture to Signoff
  • William Ruby
16:30-16:45

Closing Session & Raffle

16:45-17:30

Networking and Cocktail

8:30-8:50

Breakfeast

09:00-09:45

Infineon Keynote

09:45-10: 00

Break

10:00 - 11:30 AM CET
Increasing AMS Design Productivity and Robustness with Synopsys Custom Design Family
  • Anand Thiruvengadam

11:30-12:30

Lunch

12:30 - 01:15 PM CET
Silicon Frontline Technology Update:
1) Solving ESD-CDM challenge with full chip CDM simulation
2) Methodology to deliver efficient, reliable power devices
  • William Ruby
01:15 - 02:00 PM CET
TCAD Overview: Industry Trends and Synopsys TCAD Roadmap
  • Shela Aboud
02:00 - 02:45 PM CET
Power DTCO: Extending TCAD to the Design of Power Transistor Chips
  • Ric Borges

14:45-15:00

Break

03:45 - 04:15 PM CET
Smart Manufacturing: Process Analytics
  • Vivek/Thomas
03:00 - 03:45 PM CET
Smart Manufacturing: Product Analytics
  • Guy Cortez
10:00 - 10:45 AM CET
Automotive-Grade IP for Next-Generation Zonal Architectures
10:45 - 11:30 AM CET
Combining Neural Network Processors and DSPs to Achieve the Best AI Performance

11:30-12:30

Lunch

12:30 - 01:15 PM CET
Efficient DSP Programming with ARC MetaWare MX Development Tools
01:15 - 02:00 PM CET
Creating Design-Specific RTL with Configurable Synopsys IP Portfolio
  • Andreas Vilehaber
02:00 - 02:45 PM CET
Silicon Lifecycle Management and Monitor IPs
  • Randy Fish

14:45-15:00

Break

03:45 - 04:30 PM CET
Virtual Prototyping for Early Architecture Analysis
  • Holger Keding
16:30-16:45

Closing Session & Raffle

16:45-17:30

Networking and Cocktail