Infineon | Synopsys
Technology Symposium

Advancements in AI for EDA are playing a key role in addressing challenges posed by advanced node complexity, aggressive time-to-market targets, increasing manufacturing test costs, and the global engineering resource crunch. The session will discuss how pervasive AI is delivering significant QOR and productivity improvement across implementation, verification, and test. Solutions that will be covered include DSO.ai, VSO.ai and TSO.ai that will help  unlock new levels of productivity.

Complex, advanced-node, designs (AI, automotive, communication, high performance computing etc.) are pushing physical implementation to their limits and achieving optimal PPA is becoming a critical challenge. This session will discuss how RTL Architect enables fast and predictable RTL PPA exploration and tuning at early stage of the design flow and optimize RTL QoR , to significantly reduce RTL development cycles and de-risks the downstream implementation

This session will present updates on STA technology advances for high performance designs and evaluate the impact of robustness, variation, and process changes on PPA.

SoC designs use low power design techniques to enable support for advanced power management and demand a specialized power-aware debug solution. Easy and efficient low power debug needs to have a unified view of the design and its power intent, and an understanding and awareness of the impact of power intent on the design, in order to identify potential design-killing bugs early in the design flow.Verdi UPF Architect provides an automated flow to create and optimize the UPF from IP to SoC facilitating a single golden power intent.Due to the nature of low power design architectures and behavior, verification and signoff for low power designs are exponentially more challenging than for always-on designs. The VC LP™ static low power verification solution includes over 650 checks and offers full-chip capacity and performance for complete low power static signoff

Increasing SoC complexity demands verifying correct construction of RTL, clock domain crossing (CDC), and reset domain crossing (RDC) early in the RTL phase of development. Synopsys VC SpyGlass integrates advanced algorithms and analysis techniques that provides designers detailed information and insights about their design much earlier in the RTL phase.

Leveraging the latest formal technologies and Machine Learning techniques, Synopsys VC Formal™ has the capacity, speed and flexibility to exhaustively verify some of the most complex SoC designs, find deep corner-case design bugs, and achieve formal signoff. Natively integrated with Synopsys VCS®, Verdi®, VC SpyGlass™, VC Z01X Fault Simulation and other Synopsys design and verification solutions, VC Formal continues to innovate to solve the toughest verification challenges in the industry.

1) Review how to resolve CDM through simulation, taking account of transient effects and packaging

2)New approach to optimize designs and automatically correct EM violations

Automotive electronics and vehicle electrification, 5G/6G, hardware development for AI, and new computing are key industry drivers which impact the application and development of the Synopsys TCAD tools, from pathfinding R&D to high volume manufacturing. This track provides an overview of the Synopsys roadmap and development directions for Sentaurus TCAD, QuantumATK, TCAD-to-SPICE and DTCO solutions

Power electronics are critical to vehicle electrification, smart grid, renewable energy and other large industry segments. In this track we present the latest updates in the development of Power DTCO for the electro-thermal design of SiC and GaN power transistors. The updates include enhancements to process modeling of SiC and GaN fabrication, device simulation of large termination structures, compact model extraction, layout environment for design of unit cells and full chip, and the integration of the Silicon Frontline ETHAN and R3D tools into the Power DTCO flow

Automotive applications are becoming increasingly complex and require high levels of precision and accuracy in terms of algorithms and data formats. As algorithm complexity grows, system architects are developing their algorithms with tools such as MATLAB, which work in high-precision data formats such as half and single precision floating point. The Synopsys ARC VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of these computation intensive applications. However, powerful software development and programming tools are needed to ease DSP development and maximize application performance. We will discuss the Synopsys ARC MetaWare MX Development Tools, a complete suite of tools, SDKs, runtime software and libraries that provide everything needed to program ARC VPX DSPs, and we will provide tips and tricks on how to most effectively program your ARC VPX DSP.

As Infineon continues to expand its use of Synopsys IP, designers face the challenge of efficient and effective IP configuration and re-use. In this presentation, we will demonstrate how the Synopsys coreConsultant utility allows you to change the configuration of IP to evaluate tradeoffs between power, performance, and area. Within a graphical or command environment at your desk, coreConsultant guides you through the installation, configuration, verification, and implementation of the IP. Second, we will explain coreBuilder, which allows you to capture all the components of an IP core, including user configurable design parameters, and set the boundaries and cross dependencies of these parameters. Third, we will cover coreAssembler, which guides you through the assembly and configuration of an IP-based subsystem. Finally, we will discuss the built-in interfaces to Synopsys EDA tools such as Design Compiler and PrimeTime.