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Synopsys Sessions & Posters Spotlight
Technology experts from Synopsys are presenting multiple topics at GoMACTech 2023 to help you build mission-critical, high-performance, low-power and trusted systems. Wherever your interest focuses, from the embedded edge to the data center, Synopsys experts can help you optimize your chips, systems and security to meet mission requirements.
AI Optimized Design
Optimizing System-on-Chip Designs using AI
Manpreet Singh And Nitin Garg
SPEAKER 19.3 Adv Next Gen MicroE
Finding the optimal System-on-Chip (SoC) design parameters for a specific software application is a multi-objective design optimization problem, where competing design vectors are PASS- Power, Area, Speed (Performance) and Security. Today’s state-of-the-art method to do so is user driven simulation-based architecture exploration and optimization which is very tedious and manual intensive task. In this paper, we propose a novel Artificial Intelligence (AI) based approach which finds out the optimal set of SoC design parameters automatically by efficiently exploring the vast design space. Novelty of this solution lies in the fact that it is faster and at least as optimal as than the current approach.
Balancing Performance and Power on the AI Edge
Gordon Cooper
Poster
As AI implementations continue their move toward edge devices, there is a growing need for more efficient Neural Network processing across a broad range of performance, power and price points, leading to various processor-based implementation options. This paper will illustrate the trade-offs – including power and performance – between selecting an AI enabled DSP versus adding a dedicated AI accelerator including the newest Neural Processing Units (NPUs). Best practices in benchmarking will be covered and a review of use cases and the decisions made for applications including automotive, consumer and computer applications. The importance of software support across processors will also be covered.
RF and Digital Signal Processing
Design-Technology Co-Optimization of Power Amplifiers for 5G Applications
Nelson de Almeida Braga, Jonathan Cobb, Jingtian Fang, Binjie Cheng, Plamen Asenov, and Ricardo Borges
SPEAKER (40.1) RF Design Technologies and Techniques
This paper describes a RF Technology-Design CoOptimization (DTCO) simulation flow to support development of 5G, 6G hardware and other emerging wireless systems. The optimization flow includes Technology CAD (TCAD) simulations of fabrication processes and device electrothermal behavior, followed by extraction of SPICE compact models from TCAD results, and RF circuit-level simulations. A practical approach to assess root cause of non-linearities in Power Amplifiers is presented.
Verifying Floating-Point Digital Signal Processing Using Formal Methods
Neelabja Dutta and Ming Zhang
SPEAKER (37.2) Adv Sensors
Digital Signal Processing (DSP) processors perform high-speed numeric calculations used in both consumer electronics, industry instrumentation, as well as military and defense applications. Recent advancement in technologies, such as automated driver assistance systems (ADAS) and RADAR/LiDAR applications, have made floating-point DSP a requirement to support higher dynamic range and precision in data computation.
Formal Methods have long been used to verify functional correctness of digital systems. Its exhaustive analysis based on mathematical proof can find corner case bugs and lead to full proof of design behaviors. Recent years, datapath validation using Formal Methods have gained adoption in many application spaces, because modern CPU, GPU, AI/ML, and DSP need to process large amount of data and perform complex computations.
Multi-Die Systems
The New Era of Innovation in 3DHI Microsystems: Tools, Flows, and Methodologies
Kenneth Larsen
SPEAKER (14.2) Adv in Multi-Chip Integration
The adoption of 3D Heterogeneous Integration and advanced packaging technologies is limited in the tools and expertise required to take advantage of the manufacturing possibilities. 3DIC design collapses traditionally separate disciplines – IP, chip, and package design - into a single design team. 3DIC requires new systems methodologies that span heterogeneous design, materials, multi-physics analysis, physical implementation, and verification. 3DHI also introduces new requirements for co-design and analysis to newly integrated design teams unfamiliar with them. This paper presents recent advances and directions in tools. flows and methodologies for the new era of innovation in 3DHI microsystems.
Security and DARPA AISS
Design Data Security In Manufacturing Data Flows
James Shiely
Poster
After a VLSI design is completed and a file representing the physical design is delivered to a foundry for fabrication, substantial data processing such as Optical Proximity Correction (OPC) is performed. The transmission, storage, and transformation of the design data during manufacturing opens up several points of attack for a malicious actor to degrade or alter the design. Potential consequences could include unintended functionality, reduced yield, or reduced performance. This paper provides a description of the data flow from an initial physical design through the photomask fabrication process. It identifies attack points where a malicious actor could damage the integrity of the design. It then evaluates strategies to mitigate risks of successful attacks, as well as improving traceability to identify the point sources of attacks.
Silicon Lifecycle Management Infrastructure Pivots to Detect Security Breaches
Adam Cron and Firooz Massoudi
Poster
The potential to use embedded sensors and supporting infrastructure to detect hardware security attacks is a good use of existing device- and system-level information sources embedded in an SoC (system on chip). These integrated circuit package-level sensors and monitors have been available for some time, but their application emphasis has usually been on performance, reliability, and safety. By coupling existing and novel sensor technology with in-system and cloud-based analytics, it is possible to detect and mitigate the efforts of hardware hackers as they try to apply their skills to uncover the secrets and capabilities stored inside today’s advanced electronics. This paper will review sensors and supporting infrastructure and their capabilities to help detect and mitigate a security breach.
Mission-Critical Design and Operation
An Automated Method for Adding Resiliency to Aerospace and Defense SoC Designs
Mary Ann White
Poster
Adding safety measures to system-on-chip (SoC) designs in the form of radiation-hardened elements or redundancy is essential in making Aerospace and Defense (A&D) applications more resilient against random hardware failures that occur. Designing for safety does impact semiconductor development where these safety measures have generally been inserted manually by designers. Manual approaches can often lead to errors that cannot be accounted for. Synopsys has created a fully automated implementation flow to insert various types of safety mechanisms which can result in more robust and reliable SoC designs for A&D applications.
Superconducting Electronics
Advanced TCAD and EDA tools in Support of VLSI Superconductor Electronics Design
Robert Freeman, Jamil Kawa and Kishore Singhal
SPEAKER (19.1) Advances in Next Generation Microelectronics
Superconductor Electronics will be a critical enabling technology for a number of applications and technology leadership areas important to the Intelligence and Defense Community, including high-speed processors important in Raw Performance Compute, Energy Efficient Computing, Signal Discrimination in Fast-Big Data (SIGINT), and Efficient AI/ML Training Systems. Superconductor Electronics is also a key enabler in research towards the implementation of Scale Quantum Computing and Reversable Adiabatic Computing. Developments in Superconductor Electronics will serve as a control logic and interface foundation for emerging Quantum Information Science (QIS) devices and systems for applications in sensing, communication and information processing.
An RTL-to-GDS Flow Based on an Industrial Electronic Design Automation(EDA) Toolchain for Single Flux Quantum Circuits
Eric Mlinar, Stephen R. Whiteley, Anton Belov, Song Chen, Luca Amaru, Tong Liu, Yalan Zhang, Taufik Arifin, Min Pan, Troy Barbee, Rajinder Singh, Amir Ajami, Danny Rawlings, Arturo Salz, Robert Freeman, Scott Chase, Jamil Kawa
Poster
Josephson Junction-based superconducting circuits are promising candidates for high-speed digital electronics with dramatically lower power consumption than CMOS, as well as a potential enabler in research towards the implementation of large-scale quantum computing. In this paper, we will describe an automated flow for the creation of microcontrollers and other digital systems in the Single Flux Quantum (SFQ) technology. Starting with a Register-Transfer Level (RTL) description of the circuit, the flow integrates logic synthesis, technology mapping, timing and logic verification, library cell placement and routing, and completes with a candidate physical design for fabrication. The flow makes use of the same tools employed in leading-edge CMOS. We will examine the challenges specific to superconducting electronics (SCE) technology at the different stages in this flow. We will also report on metrics to qualify the resulting physical layout, such as circuit density and timing results.
In this paper, we will detail the adaptation of SCE libraries for the Synopsys RTL-to-GDSII flow, as well as the enhancements to the Synopsys tools for the enablement of SFQ technology. The traditional separation between clocked state registers and an unclocked combinational cloud requires special treatment for SCE, given the clocked nature of the basic logic gates. We will illustrate the flow using an SFQ library that is provided by Hypres, Inc. This library was designed and realized for the MIT Lincoln Laboratories SFQ5ee process. We will discuss the timing schemes implemented for SFQ technology, as well as the associated modifications to the flow and the library to achieve this.
Additionally, we will describe enhancements to the synthesis engine for this technology, such as accounting for the limited fanout in the SFQ libraries and minimizing the pipeline depth to optimize performance. We will discuss clock tree synthesis, as well as the signal routing methodology employed, where passive transmission line (PTL) interconnect is used exclusively. We will conclude with data on several completed example designs, reporting gate counts, chip area, congestion, and the static timing analysis of the circuit.