Josephson Junction-based superconducting circuits are promising candidates for high-speed digital electronics with dramatically lower power consumption than CMOS, as well as a potential enabler in research towards the implementation of large-scale quantum computing. In this paper, we will describe an automated flow for the creation of microcontrollers and other digital systems in the Single Flux Quantum (SFQ) technology. Starting with a Register-Transfer Level (RTL) description of the circuit, the flow integrates logic synthesis, technology mapping, timing and logic verification, library cell placement and routing, and completes with a candidate physical design for fabrication. The flow makes use of the same tools employed in leading-edge CMOS. We will examine the challenges specific to superconducting electronics (SCE) technology at the different stages in this flow. We will also report on metrics to qualify the resulting physical layout, such as circuit density and timing results.
In this paper, we will detail the adaptation of SCE libraries for the Synopsys RTL-to-GDSII flow, as well as the enhancements to the Synopsys tools for the enablement of SFQ technology. The traditional separation between clocked state registers and an unclocked combinational cloud requires special treatment for SCE, given the clocked nature of the basic logic gates. We will illustrate the flow using an SFQ library that is provided by Hypres, Inc. This library was designed and realized for the MIT Lincoln Laboratories SFQ5ee process. We will discuss the timing schemes implemented for SFQ technology, as well as the associated modifications to the flow and the library to achieve this.
Additionally, we will describe enhancements to the synthesis engine for this technology, such as accounting for the limited fanout in the SFQ libraries and minimizing the pipeline depth to optimize performance. We will discuss clock tree synthesis, as well as the signal routing methodology employed, where passive transmission line (PTL) interconnect is used exclusively. We will conclude with data on several completed example designs, reporting gate counts, chip area, congestion, and the static timing analysis of the circuit.