State of the art SoCs incorporate a plethora of analog mixed-signal (AMS) components, such as SERDES, power conditioners, converters, filters, and high-speed memory (DDR). Many of these IPs require firmware for equalization, calibration, tuning, and configuration. The designs are complex and already a challenge for hardware verification. Validation of them working under software control, pre-silicon, has been largely impossible. This creates a problem for commercial and government firms alike. This paper presents a novel solution whereby hardware-based emulation is enhanced to overcome the many limitations of current accelerated simulation technology, such as the lack of support for floating point valued signals, analog math operations, timing of intermixed analog and digital logic controls, analog output, and other requirements of AMS design verification that are not available with digital logic only emulators. DDR5 calibration serves as a demonstration of this new capability.