Synopsys Sessions & Posters Spotlight

Synopsys presented a number of sessions and posters at GOMACTech 2022. Learn more about how we address these topics for our customers who need to build mission-critical, high-performance, low-power and trusted systems from the embedded edge to the data center. 

We also hosted a special Talk with the Authors - a time with the session and poster owners.

IARPA SuperTools


An Advanced Physical Design and Verification Tool Suite for VLSI Superconducting Electronics Design
Ron Duncan, Eric M Mlinar, Sidd Devalapalli, Nisha M Johnson

Paper,

Superconducting electronics (SCE) chip design has been limited by the lack of automation and integration in EDA tools. Large, complex SCE chips in the 1 million gates / 10 million Josephson Junctions (JJ) range, cannot be successfully implemented without significant advances in design automation tools, design flows and methodologies like those developed for VLSI CMOS. This paper will discuss a state-of-the-art, integrated tool suite developed for physical design, verification, and parasitic extraction of SFQ designs at a block and full-chip level. This work has been done as a part of the IARPA SuperTools program. We will describe tools and approaches for automated layout, circuit simulation, design rule checking (DRC), layout vs. schematic (LVS) checking, parasitic extraction for post-layout simulation and design-rule-correct fill strategies that can be deployed at the VLSI scale.

Abstract 

Interconnect Analysis of Super Conducting Circuits
Greg Rollins and Aaron Barker

Poster,

Superconducting Electronics will be a critical enabling technology for a number of applications areas important to the Intelligence and Defense Community, including high-speed processors important in Raw Performance Compute, Energy Efficient Computing, Signal Discrimination in Fast-Big Data (SIGINT). As part of the IARPA sponsored SuperTools program, Synopsys is collaborating with industry and academia experts in the field of Superconducting Electronics (SCE) to develop a comprehensive set of multi level Electronic Design Automation (EDA) tools that enable the automation of digital SCE designs. In this flow logic cell and transmission line models are developed at high accuracy using specialized field solvers. The full design is then extracted as a model constructed of Passive Transmission Lines (PTLs) and circuit level (Josephson Junction / Inductor) models and simulated using HSPICE. The tools are capable of analyzing RFSQ, EEFSQ and AQFP designs.

Abstract 

Circuit Simulator for Logic Verification and Circuit Optimization in Superconducting Electronics
Sam Lo and SuperTools Team

Poster,

Energy-Efficient Rapid Single Flux Quantum (ERSFQ) and Adiabatic Quantum-Flux-Parametron (AQFP) circuits are two families of superconducting digital logic that enable ultra-low-power high speed digital systems. These circuits are designed with superconducting Josephson junction devices that require specialized tools for circuit simulation. Synopsys’ PrimeSim HSPICE, a widely used large-scale circuit simulator in the semiconductor industry, has been under development for superconducting electronics (SCE) through the IARPA SuperTools program since 2017. HSPICE has been enhanced to support Josephson junction devices through the inclusion of customized features, such as a Gaussian pulse source, a quantum phase probe, and built-in Josephson junction models, and it has demonstrated simulator capacity on circuits with over a million Josephson junctions. Based on the foundation of HSPICE SCE features, two new solutions for SCE digital design are implemented: logic validation and parametric yield optimization. In this paper, we demonstrate logic validation and yield optimization on sample SCE gates.

Abstract 

Security and DARPA AISS


Automatic Implementation of Secure Silicon (AISS) Program: A Cloud-Based EDA SoC Design Flow for Optimally Balancing Power, Area, Performance and Security In An Untrusted IP Supply Chain
Dale Donchin

Poster,

The Automatic Implementation of Secure Silicon (AISS) Program is a DARPA-funded project led by Synopsys as a Prime Contractor, addressing the need for an automated EDA design flow capable of rapid production of State-of-the-Art semiconductor SoC designs, optimally balancing power, area, performance, and security depending on the end application. Facing a large, dynamic and complex untrusted supply chain, security within the SoC design flow is an increasing concern to Industry, the Government and Defense organizations alike. The intent of the AISS program is to research, develop and implement useful technology that fortifies key protections against security vulnerabilities at risk within the EDA flow in a cost-effective and time-efficient manner. To enable designer controllable security trade-offs and other design parameters, the AISS program developed new innovations, incorporated techniques to counter reverse-engineering threats and tamper injection attacks and estimate side-channel leakage, while also addressing manufacturing issues in an untrusted supply chain.

Abstract 

AMS Emulation and DARPA POSH​


AMS Emulation Comes to the Rescue of Rapid DDR Calibration Verification Pre-Silicon
Dale Donchin and Team

Poster,

State of the art SoCs incorporate a plethora of analog mixed-signal (AMS) components, such as SERDES, power conditioners, converters, filters, and high-speed memory (DDR). Many of these IPs require firmware for equalization, calibration, tuning, and configuration. The designs are complex and already a challenge for hardware verification. Validation of them working under software control, pre-silicon, has been largely impossible. This creates a problem for commercial and government firms alike. This paper presents a novel solution whereby hardware-based emulation is enhanced to overcome the many limitations of current accelerated simulation technology, such as the lack of support for floating point valued signals, analog math operations, timing of intermixed analog and digital logic controls, analog output, and other requirements of AMS design verification that are not available with digital logic only emulators. DDR5 calibration serves as a demonstration of this new capability.

Abstract 

Mission-Critical Design and Operation


Building a Sensor Infrastructure to Detect Security Breaches
Adam Cron, Firooz Massoudi

Poster,

This paper will delve into the potential to leverage embedded sensors and supporting infrastructure to detect hardware security attacks. Integrated circuit package-level sensors and supporting infrastructure have been available for some time, but their application emphasis has been on performance and reliability. By coupling sensor technology with in-system and cloud-based analytics, it may be possible to detect and mitigate the efforts of hardware hackers as they try to apply their skills to uncover the secrets and capabilities stored inside today’s advanced electronics. We will elaborate on the capabilities of today’s sensors and supporting infrastructure, and delve into the potential to leverage these structures to detect hardware security attacks. We will also illuminate structured automation allowing the gathering and analysis of data to detect security attacks, and tune system constraints such that a system’s reaction to and mitigation of such an attack is likely an appropriate response.

Abstract 

Failure Prediction of Field-Deployed Mission Critical Chips using AI-Powered Technologies
Venki Venkatesh and Team

Live Session,

Mission critical chips are essential to the survival of an entire business or operation in defense, space, hospital systems and even in commercial sectors. When mission critical chips fail, they can compromise the entire mission. In this work, we present methods to predict failure of mission critical chips to take remedial actions and prevent the compromise of the mission. We suggest to track mission critical chips in real time through embedded sensors and predict their state-of-health and future potential failures with artificial intelligence. Our work paves the way for remote failure prediction of mission critical chips deployed in the field for preventive maintenance.

Abstract 

Leveraging Lessons Learned from Automotive Design Reliability in Aerospace and Defense Applications
Meirav Nitzan and Ian Land

The automotive industry has the scale to invest heavily in reliable, safe, and secure microelectronic design innovations, especially related to autonomous vehicles and assisted driving. Similarly, the aerospace and defense (A&D)industry has also been making similar investments, but does not operate at the same scale. The aligned needs of these industries can help benefit both.The lessons learned in high-reliability automotive design can be leveraged to improve the reliability, safety, and security of A&D applications, as well as the radiation tolerance of semiconductor devices. In this paper we introduce all the aspects of reliable automotive design, its applicability to A&D, and focus on techniques used for automotive functional safety and their applicability to A&D.

Abstract 

Simulation and Prototyping


Design and Simulation of an Active Thermal Cooling System for Lithium-ion Battery Pack for Pulsed Power Loads
Bryan Kelly

Poster,

Excessive heating plays a key role to limit the performance, reliability and lifetime of batteries applied to pulse power systems. In this paper, a high-level simulation study will be presented to illustrate virtual prototyping of an active cooling system for maintaining the temperature of an Li-ion battery pack and pulse driven high-power laser load. Active cooling designed as a complementary system, utilizes a coolant circulated via a motor driven thermohydraulic pump, pipes, a crossflow heat exchanger and cooling plates resident against the battery pack and laser assembly. A thermostat coupled to a valve maintains the temperature of the dynamic thermal Li-ion battery pack within a narrow but optional Goldilocks region of operation. In face of range of ambient temperatures, and heavy load scenarios, an active liquid cooled system gives the most effective and efficient thermal management to ensure safety and optimal battery life, validated through stress and statistical simulation analyses.

Abstract 

Performance Comparison Of Si-IGBT, SiC-MOSFET, And GaN-HEMT Using Virtual Prototype Of An Electric Vehicle Inverter Design
Bryan Kelly and Datsen Tharakan

Poster,

Wide-bandgap (WBG) devices such as Silicon Carbide (SiC) and Gallium Nitride (GaN) are gaining tremendous attention in power electronics designs because of rapid advancements in manufacturability and commercial availability. Aerospace and automotive applications are driving their focus towards WBG devices due to their high efficiency, improved performance, longevity, and capability to operate in harsh environments. The large bandgap of these devices enables a higher breakdown voltage. They are also intrinsically radiation-hardened (rad-hard) and offer a theoretical junction temperature operation of up to 600°C. The high thermal conductivity of these devices helps with lower cooling requirements. The size and weight of the passive and magnetic components in the rest of the power electronics design are reduced due to the fast switching capability of WBG devices. Therefore, WBG devices are increasingly replacing their silicon counterparts in high voltage, high switching frequency, and high-temperature applications, and promise lower energy consumption and lower emission for the automotive and aerospace industries. In this paper, the performance of commercially available Si-IGBT, SiC-MOSFET, and GaN-HEMT devices are compared with the help of a virtual prototype of an electric vehicle inverter design that drives a permanent magnet synchronous motor (PMSM). Efficiency curves of three inverter designs are compared under three different load conditions. The improved performance of WBG devices enables an extended drive range for battery-driven vehicles. The electrical and thermal stress handling capability of WBG devices are validated using Stress Analysis. The dynamic junction temperature of the WBG devices is simulated under various load conditions, and the advantages of lower cooling requirements are discussed in this paper.

Abstract 

RF and Digital Signal Processing


Digital Signal Processing Goes Floating-Point
Markus Willems, Tayo Adesanya, Steve Cox

Poster,

Moving from a digital signal processing (DSP) focused FPGA-based implementation to an ASIC-based design comes with many tradeoffs. One of them is the lack of ASIC hardware re-programmability. For an ASIC, its hardware DSP capabilities are decided at tape out, and redesign is costly and time consuming. A software enabled and programmable DSP processor will be a critical enabling technology for a large number of applications and technology leadership areas important to the Government and Defense communities. With the adoption of software programmable DSP processors comes the option to describe applications using floating point arithmetic, and to implement it using a processor with native floating point support. This paper covers the motivation for using floating point arithmetic, and why modern DSP processor architectures enable such floating point operations even for most demanding embedded applications.

Abstract 

Programmable ASIC: The Next Frontier in Embedded Signal Processing
Michael Parker - Raytheon Technology

Poster,

Many defense applications require extensive digital signal processing, often in SWaP constrained environments. The typical approach is to use COTS components, very frequently FPGAs, to support this. When the SWaP constraints are too rigorous for FPGA solutions, then custom ASICs are typically developed. Unlike commercial, defense applications rarely have the volume applications to achieve cost savings by amortizing the ASIC development cost and effort. Defense ASICs are usually developed in response to SWaP limitations of programmable alternatives. Further, these ASICs are typically coded at RTL level, are fixed function and support only a specific program, and do not allow for feature upgrades once deployed in a system. A better solution for many applications is the “programmable ASIC”. This sounds like an oxymoron, but this paper will explore how this approach can achieve the power consumption of a custom ASIC while supporting the programmability of an FPGA.

Abstract