Power Handling during Test is an important factor that needs to be considered during chip design, silicon bring-up, and In-System Testing. In this tutorial, we will start by listing the importance of power and the different problems faced with poor power intent. We will then proceed to give an overview of different power aspects related to test, from RTL implementation to in-system validation, and how each step can impact the overall performance. Next, we will introduce the different DFT techniques for design that help with better power planning producing optimized quality of results (QoR). Finally, we will present data sets on how each of the listed techniques implemented on real designs give the desired results.

The time required for testing silicon defects continues to rise as design complexity and transistor count increases in-line with Moore’s Law. Structured test, particularly scan compression, assists with reducing the amount of time and effort involved. Furthermore, the associated design-for-test (DFT) is often reusable for determining the root cause of defective silicon behavior. However, new challenges associated with higher system integration, such as 3D-IC and chiplet packaging technologies, and shrinking time-to-market, requires a new approach to achieve low defect levels and gain understanding of defective or abnormal behavior This relatively new approach is known as Silicon Lifecycle Management (SLM) and enables testing  and analysis throughout the different silicon life phases, and utilized analytics (diagnostics) to improve each phase from design to in-field operation.