Digital Design Technology Symposium

October 5, 2021
A Virtual Experience

A Must-Attend Event

HPC, 5G, AI, Automotive: market segments like these are presenting new challenges to ASIC and SoC designers. Synopsys is focused on delivering a continuous stream of innovative solutions with future-proof technologies to address issues such as greater energy efficiency, improved power-performance-area, faster time to market, functional safety, security, and yield optimization. The Synopsys Digital Design Technology Symposium showcases design solutions to the industry’s most compelling and topical challenges.

With something of interest for a broad range of market segments, drop in and see how Synopsys’ innovative solutions can help with your next design. Whether you are targeting improved power, performance and area, yield, time-to-market or all of the above, recent advances in Synopsys’ Fusion Design Platform solutions can help you meet your digital design goals. You will gain new insights from Synopsys R&D experts, users, and partners on integrated, end-to-end solutions being used to achieve industry-leading QoR and productivity in key areas. 

Who Should Attend?

The Digital Design Technology Symposium 2021 virtual experience is aimed at SoC designers and managers, especially those facing new design challenges driven by rapidly growing and emerging vertical segments for high-performance computing (HPC), 5G, mobile, automotive and AI applications.

Register Now

Missed #DDTS2021 live? No worries, on-demand access is available:

Tune in to hear about:,

  • How to improve power, performance, and area (PPA), yield, and time-to-market
  • New insights on the integrated, end-to-end solutions used to achieve industry leading QoR and productivity
  • Recent advances on Synopsys’ Fusion Design Platform

Key Topics

Keynote Spotlight

Boosting Productivity and Robustness in the SysMoore Era with a Triple-play of Hyperconvergency, Analytics, and AI Innovations

Tuesday, October 5 | 09:00 AM PDT

The SysMoore Era can be characterized as the widening gap between classic Moore’s Law scaling and increasing system complexity. System-on-a-chip complexity has now fallen by the wayside to systems-of-chips with the need for smaller process nodes, and multi-die integration. With engineers now handling not just larger chip designs but systems comprised of multiple chips, the focus on user productivity and design robustness becomes a major factor in getting designs to market in the fastest time and with the best possible PPA. Combining a hyperconvergent design flow with smart data analytics and AI-based solution space exploration provides a huge benefit to the engineer tasked with completing these systems. In this presentation Shankar will outline the challenges and the road to a triple-play solution that gets design engineers out of their late inning jams.

Shankar Krishnamoorthy
General Manager, Digital Design Group
Nigel Toon
Co-Founder & CEO

Agents of Change: How New Approaches to Processor Design are Unlocking New Possibilities in AI

Tuesday, October 5 | 09:30 AM PDT

Artificial intelligence has made remarkable progress in recent years, enabled – in part by the apparent suitability of the GPU for AI computation. Technology, however, has a long history of inclining towards the capabilities of the available tools. Increasingly, AI innovators are looking to break out of those constraints and explore more advanced AI techniques. Unlocking these requires a new type of processor, specifically designed for the idiosyncrasies of machine intelligence compute. Graphcore co-founder and CEO Nigel Toon discusses how his company’s Intelligence Processing Unit (IPU) is opening up these new possibilities, as well as accelerating today’s most widely used applications.

Meet the Technologists

Solaiman Rahim

Group Director R&D
Energy Efficient Design Expert

Vishal Khandelwal

Synopsys Scientist
ML/AI & 3DIC Expert

Ed Huijbregts

Group Director R&D
FuSa Automation

Dirk de Vries

Director, R&D
Silicon Lifecycle Management Expert

Henry Sheng

Group Director R&D
HPC & Advanced Technology Expert

Adam Cron

Distinguished Architect
Test Innovations Expert

Breakout Sessions

Designing for the Technology Curve

10:00 - 10:20 AM

High Performance Computing Technology for the Exascale Era

Rajit Seahra, AMD

To solve some of the toughest challenges in the world today, supercomputers simulate, model, and advance the understanding of the interactions underlying the science of weather, sub-atomic structures, genomics, physics, and more. In this session, design technology expert from AMD will discuss the unique characteristics and requirements of HPC designs, and how Synopsys Fusion technology enabled designers to deliver the AMD HPCs driving a new era in the data center.

10:20 - 10:40 AM

Designing Energy Efficient Arm®v9 Architecture CPUs with Synopsys Fusion Compiler Full-Flow

Haroon Gauhar, Sr. Principal Engineer, Arm
Brian Millar, Principal Application Engineer, Synopsys

Arm’s next-generation advanced CPU processors continue to push the performance and energy efficiency boundaries, as technology nodes continue to grow in enormous complexity. At the same time, design development cycles tied to new market-opportunities are constrained to shorter cycles than at previous nodes. Given the high design-complexity in play, targeting the highest possible performance and market-defining energy-efficiency levels lead to multiple challenges designers must mitigate during the RTL and silicon flow.
Arm and Synopsys collaborated to use Fusion Compiler’s native, high-capacity, hierarchical-design capabilities and convergent signoff-accurate physical-aware Tweaker ECO on the latest Arm®v9 CPUs to deliver superior design closure and significantly faster runtimes, all without compromising the achievable FMax or mW/GHz goals. The presentation will highlight new methodologies and technologies available in Fusion Compiler that allow designers to meet or exceed their challenging design goals and provide the fastest path to superior design closure. Some of the technologies discussed are: Fusion Compiler’s vector-based optimizations with Hierarchical H-Tree and Multi-Source Clock Tree Synthesis, combined with convergent PrimeTime Signoff Accurate Tweaker ECO Closure solution.

10:40 - 11:00 AM

Ultimate R2N PPA Consolidation by Fusion Compiler UPS Flow

Yukka Huang, Will Lin, MediaTek

Performance/Power/Area consolidation is a legacy challenge to digital IC design flow. Take two cases as example. Case1: at synthesis stage, over-constraint is a common solution to secure PPA quality till place-and-route stage. However, Over-constraint can also lead pessimistic PPA result. Case2: traditional synthesis flow can't consider clock tree synthesis. This kind of situation can make a natural gap between synthesis and physical design as well and get an optimistic PPA result at synthesis stage. Above examples can introduce PPA un-stable through whole implementation flow. In this work, we will demonstrate how Fusion Compiler UPS flow consolidate PPA in decent range from synthesis to post-route.

Innovation in Critical Applications

10:00 - 10:20 AM

GlobalFoundries® 22FDX® Digital Automotive Flow

Nidhish Gaur, GlobalFoundries

The presentation introduces GlobalFoundries® 22FDX® as the technology and design platform of choice for the next generation of automotive designs. It focuses on how the 22FDX® AG1 Automotive digital design platform supports ISO26262 functional safety (FuSa) requirements. Synopsys® Design Compiler® (DC-NXT) and IC Compiler® II toolset based “safety-aware digital design flow” is described to introduce FuSa features on a safety critical design, implemented with GF® 22FDX® based Synopsys® Automotive Grade 1 (AG-1) 9-track std-cell library. The FuSa features covered are “TMR (triple mode redundancy), DMR (double mode redundancy), Fault-tolerant flops, DCLS (dual core lock step) and 100% (or high) RVI (redundant via insertion)”. Finally, implementation results are summarized, with key focus on the impact assessment of FuSa feature introduction on the PPA results.

10:20 - 10:40 AM

Fast and Cost Effective Analysis to Improve System Reliability

Ghani Kanawati, Arm

Reliability, availability and serviceability is a major concern for cloud applications. Many semiconductor and system companies put emphasis on adding hardware duplication, a costly solution to detect and mitigate failures. A deep analysis of the design can identify the portions of the design that can cause the system to behave unpredictably in the presence of soft errors. Statistical analysis based on probability of error propagation in the design can be performed in large complex systems such as the ones in cloud applications before any testbenches are available. We will present our findings based on the static analysis approach used in TestMAX FuSa to quickly identify the registers most vulnerable to soft errors early in the design development.


10:40 - 11:00 AM

Automated FuSa Methodology for Reliable Automotive Designs in Renesas

Osamu Nakanishi, Senior Manager, Renesas Electronics

Osamu Nakanishi of Renesas Electronics Corporation explains the unique reliability challenges and requirements for their automotive MCU and R-Car SoC designs. He will highlight how Renesas co-developed the automated, native functional safety (FuSa) support available in Fusion Compiler for Dual Core Lock Step (DCLS) implementation with Synopsys to deliver highly reliable and safe automotive designs.

11:15 - 11:35 AM

Physical and Timing-aware RTL Power Exploration

Wayne Szeto, Senior Component Design Engineer, Intel Corporation

One of the biggest problems with RTL power estimation is accuracy comparing against sign-off power. If the estimation is not accurate, designers lose confidence in the tool. There are multiple factors that make power estimation at the RTL level challenging. Clock tree modeling is not accurate at the RTL level because CTS is only done during implementation. Clock tree power contributes up to 30% of the overall power for some workload. Estimation without timing and physical awareness also causes power miscorrelation. Additionally, glitch power cannot be accurately calculated without timing information. Finally using different synthesis engines between RTL power estimation and implementation also contributes to miscorrelation. Synopsys offers a powerful tool to help address most of the challenges we face today. The tool is timing and physical aware, models clock tree topologies as actual implementation, and glitch power can be calculated with delay-shifting. This presentation covers power estimation results from two projects, including glitch power analysis, and ways to explore power reduction opportunities.

11:35 - 11:55 AM

Utilizing RedHawk Analysis Fusion to Relieve Voltage Drop Issues at 5nm and Below

Jinwei Zeng, Senior IC Backend Engineer, SaneChips​

With the downscaling of standard cells at 5nm and below, the risk of increasing local power density and voltage drop on the PG network has attracted a lot of attention. In this presentation we review how the Synopsys RedHawk Analysis Fusion power integrity flow enables Sanechips to reduce voltage-drop violations in advanced 5nm and 3nm designs with minimum impact to timing QoR. Potential PG network issues are detected early during implementation, followed by optimized voltage-drop-aware placement, CTS, and routing in Synopsys Fusion Compiler. With the application of the RedHawk Analysis Fusion flow, the voltage drop issues on PG network can be revealed and fixed early, and thus significantly reducing the turnaround time for the design cycle.

11:55 AM - 12:15 PM

It’s a Dynamic World – Managing Dynamic Power with Synopsys’ End-to-End Solution for Energy Efficient Design

Godwin Maben, Synopsys Fellow, Strategy & System Architects Group, Synopsys

At advanced FinFET nodes dynamic power has become the dominant component of the total power consumed by SoC designs. Managing dynamic power requires the use of low power design techniques along with the selection of right vectors derived from software workloads. This session will focus on how Synopsys’ end-to-end solution for energy efficient design enables designers to analyze and optimize dynamic power from RTL to signoff with vectors derived from software workloads.

11:15 - 11:35 AM

Power-aware ATPG Using SignOff Models


Power-aware ATPG has been a staple of the IC manufacturing community for many years. Historically, relying on weighting functions to drive the metrics of pattern generation has served the community well to help compose pattern sets that did not cause undue IR-drop during pattern application which could lower device yield. But larger reticle sizes, on-chip variation, and a refined focus on yield have led to more advanced methodologies. This presentation illuminates promising automation developed in collaboration with MediaTek, which combines the sign-off models from PrimePower with the fast calculation algorithms of TestMAX™ ATPG to generate fewer patterns with higher coverage that don’t exceed the IR-drop limits.

11:35 - 11:55 AM

Boost Coverage and Reduce Pattern Count with TestMAX Advisor

Jialiang Li, DFT Manager, SaneChips​
Alex Yu, Test Solution Manager, Synopsys​

Test points are an under-utilized design-for-test technique to boost coverage and reduce the number of test patterns required to achieve fault coverage targets. This presentation will provide a brief overview of TestMAX Advisor to analyze RTL and gate-level designs to determine the most impactful locations to insert test points. Sanechips will discuss a complete overview of their flow, showcasing their success with test point insertion. Finally, this presentation will teach you how to use TestMAX tools to quickly deploy test points with a one-step method that automatically combines analysis and implementation within Synopsys synthesis products to improve ATPG and logic BIST results.


11:55 AM - 12:15 PM

Cell-aware Defect Detection - Robust vs. Non-Robust Detection

Ruifeng Guo, Sr. Staff Engineer, Synopsys

The standard approach is to target defects between cells. These “inter-cell faults” are always assigned to the input and output pins of cell instances. Cell-aware fault model is used to find the physical defects that originate inside the cells. The two ways of detection are Robust and Non-Robust. In collaboration with Elmos, this presentation compares the cell-aware test coverage data on over seven designs.

12:30 - 12:50 PM

Accelerating PPA Improvements with Scalability

Milind Mahajan, Intel

Achieving predictable convergence for RTL2GDS design is heavily dependent on design input collaterals quality and is susceptible to changes in RTL, floorplan, stdcell/EBB libraries, design constraints etc. This problem gets harder for designing multi-million instance SOC/IPs being developed on leading process nodes and includes new SOC/IP architectures where changes in RTL, floorplan are large and constant. Using ML/AI based design optimization through AI, we can simplify optimization of key metrics and explore various tradeoffs. Synopsys’ AI solution works in conjunction with APR implementation tools and provides all necessary capabilities to permute various tool options, design constraints, design specific optimization strategy/recipe variations and learn from each APR run to predict and optimize the settings for achieving target PPA goals. With targeted use-model of AI based PPA optimization, we demonstrated better PPA on top of best engineer optimized convergence recipe on few critical designs in our SOC. In this presentation, we discuss our case study of scaling up the PPA optimization use model to multiple designs adding up to more than half of the SOC and demonstrating larger PPA benefit at full SOC level. We also discuss new features and use models with Synopsys’ AI solution to help with scalability for PPA optimization across multiple designs.

12:50 - 01:10 PM

PrimeTime Path Reporting and ECO Efficiency Improvement Using Machine Learning PBA

Tusharkant Mishra, Associate Technical Director, Samsung India

PBA path reporting is an integral part of STA analysis. Exhaustive PBA runtime can be long, particularly in the pre-signoff phase where the design has many violations. PBA path mode is not sign-off safe and can mask violations. During initial ECO iterations of the design cycle, a high fix rate is desirable for timing violations and also there are good opportunities for power recovery. Exhaustive PBA based timing/power ECO ensures most accurate fixing and avoids GBA mode over-fixing, however it is highly runtime intensive due to the high number of violating paths in the initial iterations.
User requirements to improve on existing flows and solutions were - a simple User Interface, minimal runtime penalty even with many violations and an option to trade QoR for runtime improvements in earlier cycles of ECO and STA reporting.
PrimeTime Machine Learning PBA improves PBA runtimes across the design with a single PBA setting. It is sign-off safe by construction and trades-off runtime vs. accuracy automatically as TNS reduces. In this paper, we will talk about how PrimeTime ML-PBA improves overall Turn Around Time of STA runs and ECO cycles while preserving the benefits of Exhaustive PBA.

01:10 - 01:30 PM

Enabling Next-generation of HPC Designs Using Samsung’s Multi-die (3DIC) Integration Solution

Yoonjae Hwang, Principal Engineer, Samsung

Increased high-performance computing needs – driven by datacenter, AI, 5G and automotive applications – demands innovations to address design size scalability and complexity while meeting PPA, cost and TTM constraints. Heterogeneous integration or the multi-die chiplets-based design is gaining in importance to address these challenges and extend the semiconductor roadmap beyond Moore’s Law. Samsung Foundry and Synopsys, long-time collaborators, have developed state-of-the-art solutions to accelerate multi-die design. In this presentation, Samsung will provide insights into the unique challenges faced by customers in deciding the most desirable system configuration for advanced 2.5/3D packaging for their specific design requirements. They will share highlights of the Samsung Chiplet Advanced Platform Engine (SCAPE) that provides customers with an innovative platform to realize the most optimal architecture in the context of performance and cost. Samsung will also share the collaboration work with Synopsys on 3DIC Compiler that maximizes the benefits of SCAPE by providing a comprehensive, integrated co-design and analysis solution to enable customers to achieve the targets with greater efficiency and faster time to production.

12:30 - 12:50 PM

SCAN Test Through Functional High-speed Interfaces

Michael Braun, Product Marketing for Semiconductor Test, Advantest

Overall design size and complexity combined with modern ATPG fault models leads to ever-increasing SCAN test data volumes on ATE. Test pattern run times grew from seconds to minutes per device, and conventional scan test access paths are part of the problem: A low-speed, GPIO-based parallel interface may not be sufficient anymore to transfer massive amounts of test data in a reasonable amount of time. In addition, SCAN test patterns are being deployed in System-Level Test (SLT) or even for regular ‘health checks’ of the device in the end application. To enable this, a standard interface like USB or PCIe must be used to transfer the test content, since the parallel test port used on ATE is typically not accessible. This paper presents how to enable SCAN test through functional HSIO on V93000 production ATE: A new type of digital instrument stores all the test data and connects to the device through a standard HSIO I/F using its native protocol. Synopsys High-Speed Access & Test (HSAT) IP inside the device drives the test data through the scan chains. Result evaluation and post-processing is done on the ATE instrument, supported by a TestMAX ALE embedded software component running locally on the tester. Using this new methodology enables a significant increase in the test content transfer rate on production ATE, using widely available and standardized high-speed interfaces with a relatively low pin count. This also enables the transfer of test content between different test insertions, like ATE and SLT, as well as the deployment of production test patterns for in-system test usage.

12:50 - 01:10 PM

Volume Diagnostic Analysis for Advanced Process Improvement

James Guan, Intel

As advanced processes get more complex, high-quality diagnosis and defect identification becomes more challenging and time consuming. Synopsys offers powerful tools to help failure analysis and product engineers quickly identify significant systematic, design related issues delaying products from ramping to full production. Key failure mechanisms found in the design are quantified, prioritized and then submitted as FA samples based on volume diagnostic analysis. This presentation demonstrates one such Synopsys application which specializes in root causing scan and memory failures during scan ATPG and memory BIST testing to enable faster product ramp on advanced process nodes.

01:10 - 01:30 PM

In-chip Path Margin Analysis for HPC Adaptive Voltage Schemes and Power Optimization

Steve Crosher, Synopsys

Advanced node technologies underpin the capabilities offered by High Performance Computing. Challenges associated with the physical management of multi-core architectures within high gate density, large scale designs are well documented. Chip power consumption does not only require management but also requires optimizing in order to deploy competitive products and meet user experience expectations. The reduction of voltage supply throughout a chip is attractive, with any reduction saving dynamic power proportional to the square of the supply voltage with further potential static power savings due to lower die temperatures. The question is therefore, by how much can I reduce supply voltages whilst maintaining sufficient functionality and performance of embedded logic during operational mode? 
The set-up and hold timing margins, or ‘slack’, of digital logic is sensitive to supply. Therefore, an opportunity is created to apply timing path monitors at multiple locations within a chip that support adaptive voltage scaling schemes for power optimization tailored to each individual device. Such monitoring should have a small area footprint and be non-intrusive, running in parallel to the functional mode of the device. In this session an overview will be provided of the current requirements of the chip design community, path margin monitor implementation and how such monitors sit within the wider scope of analytics applied to silicon lifecycle management. 

Digital Design Technology Symposium | Synopsys