Rajit Seahra, AMD
To solve some of the toughest challenges in the world today, supercomputers simulate, model, and advance the understanding of the interactions underlying the science of weather, sub-atomic structures, genomics, physics, and more. In this session, design technology expert from AMD will discuss the unique characteristics and requirements of HPC designs, and how Synopsys Fusion technology enabled designers to deliver the AMD HPCs driving a new era in the data center.
Haroon Gauhar, Brian Millar, Arm
TBD - Details coming soon.
In this session, speaker from Synopsys will discuss the journey to achieving best design results at 3nm and below technology nodes, and how EDA solutions combined with IP/library expertise and AI/ML technologies, paved an accelerated path to optimum design quality.
Nidhish Gaur, GlobalFoundries
The presentation introduces GLOBALFOUNDRIES® 22FDX® as the technology and design platform of choice for the next generation of automotive designs. It focuses on how the 22FDX® AG1 Automotive digital design platform supports ISO26262 functional safety (FuSa) requirements. Synopsys® Design Compiler® (DC-NXT) and IC Compiler® II toolset based “safety-aware digital design flow” is described to introduce FuSa features on a safety critical design, implemented with GF® 22FDX® based Synopsys® Automotive Grade 1 (AG-1) 9-track std-cell library. The FuSa features covered are “TMR (triple mode redundancy), DMR (double mode redundancy), Fault-tolerant flops, DCLS (dual core lock step) and 100% (or high) RVI (redundant via insertion)”. Finally, implementation results are summarized, with key focus on the impact assessment of FuSa feature introduction on the PPA results.
Ghani Kanawati, Arm
Reliability, availability and serviceability is a major concern for cloud applications. Many semiconductor and system companies put emphasis on adding hardware duplication, a costly solution to detect and mitigate failures. A deep analysis of the design can identify the portions of the design that can cause the system to behave unpredictably in the presence of soft errors. Statistical analysis based on probability of error propagation in the design can be performed in large complex systems such as the ones in cloud applications before any testbenches are available. We will present our findings based on the static analysis approach used in TestMAX FuSa to quickly identify the registers most vulnerable to soft errors early in the design development.
Osamu Nakanishi, Senior Manager, Renesas
Osamu Nakanishi of Renesas Electronics Corporation explains the unique reliability challenges and requirements for their automotive MCU and R-Car SoC designs. He will highlight how Renesas co-developed the automated, native functional safety (FuSa) support available in Fusion Compiler for Dual Core Lock Step (DCLS) implementation with Synopsys to deliver highly reliable and safe automotive designs.
Wayne Szeto, Senior Component Design Engineer, Intel Corporation
One of the biggest problems with RTL power estimation is accuracy comparing against sign-off power. If the estimation is not accurate, designers lose confidence in the tool. There are multiple factors that make power estimation at the RTL level challenging. Clock tree modeling is not accurate at the RTL level because CTS is only done during implementation. Clock tree power contributes up to 30% of the overall power for some workload. Estimation without timing and physical awareness also causes power miscorrelation. Additionally, glitch power cannot be accurately calculated without timing information. Finally using different synthesis engines between RTL power estimation and implementation also contributes to miscorrelation. PrimePower RTL addresses most of the challenges we face today. The tool is timing and physical aware, models clock tree topologies as actual implementation, and glitch power can be calculated with delay-shifting. It also uses the same fast compile engine as the construction tool, Fusion Complier. This presentation covers power estimation results from two projects, including glitch power analysis, and ways to explore power reduction opportunities.
Jinwei Zeng, Senior IC Backend Engineer, SaneChips
With the downscaling of standard cells at 5nm and below, the risk of increasing local power density and voltage drop on the PG network has attracted a lot of attention. In this presentation we review how the Synopsys RedHawk Analysis Fusion power integrity flow enables Sanechips to reduce voltage-drop violations in advanced 5nm and 3nm designs with minimum impact to timing QoR. Potential PG network issues are detected early during implementation, followed by optimized voltage-drop-aware placement, CTS, and routing in Synopsys Fusion Compiler. With the application of the RedHawk Analysis Fusion flow, the voltage drop issues on PG network can be revealed and fixed early, and thus significantly reducing the turnaround time for the design cycle.
Godwin Maben, Synopsys Fellow, Strategy & System Architects Group, Synopsys
At advanced FinFET nodes dynamic power has become the dominant component of the total power consumed by SoC designs. Managing dynamic power requires the use of low power design techniques along with the selection of right vectors derived from software workloads. This session will focus on how Synopsys’ end-to-end solution for energy efficient design enables designers to analyze and optimize dynamic power from RTL to signoff with vectors derived from software workloads.
Power-aware ATPG has been a staple of the IC manufacturing community for many years. Historically, relying on weighting functions to drive the metrics of pattern generation has served the community well to help compose pattern sets that did not cause undue IR-drop during pattern application which could lower device yield. But larger reticle sizes, on-chip variation, and a refined focus on yield have led to more advanced methodologies. This presentation illuminates promising automation developed in collaboration with MediaTek, which combines the sign-off models from PrimePower with the fast calculation algorithms of TestMAX™ ATPG to generate fewer patterns with higher coverage that don’t exceed the IR-drop limits.
Jialiang Li, DFT Manager, SaneChips
Alex Yu, Test Solution Manager, Synopsys
Test points are an under-utilized design-for-test technique to boost coverage and reduce the number of test patterns required to achieve fault coverage targets. This presentation will provide a brief overview of TestMAX Advisor to analyze RTL and gate-level designs to determine the most impactful locations to insert test points. Sanechips will discuss a complete overview of their flow, showcasing their success with test point insertion. Finally, this presentation will teach you how to use TestMAX tools to quickly deploy test points with a one-step method that automatically combines analysis and implementation within Synopsys synthesis products to improve ATPG and logic BIST results.
Milind Mahajan, Intel
Achieving predictable convergence for RTL2GDS design is heavily dependent on design input collaterals quality and is susceptible to changes in RTL, floorplan, stdcell/EBB libraries, design constraints etc. This problem gets harder for designing multi-million instance SOC/IPs being developed on leading process nodes and includes new SOC/IP architectures where changes in RTL, floorplan are large and constant. Using ML/AI based design optimization through DSO.ai, we can simplify optimization of key metrics and explore various tradeoffs. DSO.ai works in conjunction with APR implementation tools like Fusion Compiler and provides all necessary capabilities to permute various tool options, design constraints, design specific optimization strategy/recipe variations and learn from each APR run to predict and optimize the settings for achieving target PPA goals. With targeted use-model of DSO.ai based PPA optimization, we demonstrated better PPA on top of best engineer optimized convergence recipe on few critical designs in our SOC. In this presentation, we discuss our case study of scaling up the PPA optimization use model to multiple designs adding up to more than half of the SOC and demonstrating larger PPA benefit at full SOC level. We also discuss new features and use models with DSO.ai to help with scalability for PPA optimization across multiple designs.
Tusharkant Mishra, Associate Technical Director, Samsung India
PBA path reporting is an integral part of STA analysis. Exhaustive PBA runtime can be long, particularly in the pre-signoff phase where the design has many violations. PBA path mode is not sign-off safe and can mask violations. During initial ECO iterations of the design cycle, a high fix rate is desirable for timing violations and also there are good opportunities for power recovery. Exhaustive PBA based timing/power ECO ensures most accurate fixing and avoids GBA mode over-fixing, however it is highly runtime intensive due to the high number of violating paths in the initial iterations.
User requirements to improve on existing flows and solutions were - a simple User Interface, minimal runtime penalty even with many violations and an option to trade QoR for runtime improvements in earlier cycles of ECO and STA reporting.
PrimeTime Machine Learning PBA improves PBA runtimes across the design with a single PBA setting. It is sign-off safe by construction and trades-off runtime vs. accuracy automatically as TNS reduces. In this paper, we will talk about how PrimeTime ML-PBA improves overall Turn Around Time of STA runs and ECO cycles while preserving the benefits of Exhaustive PBA.
Yoonjae Hwang, Principal Engineer, Samsung
Increased high-performance computing needs – driven by datacenter, AI, 5G and automotive applications – demands innovations to address design size scalability and complexity while meeting PPA, cost and TTM constraints. Heterogeneous integration or the multi-die chiplets-based design is gaining in importance to address these challenges and extend the semiconductor roadmap beyond Moore’s Law. Samsung Foundry and Synopsys, long-time collaborators, have developed state-of-the-art solutions to accelerate multi-die design. In this presentation, Samsung will provide insights into the unique challenges faced by customers in deciding the most desirable system configuration for advanced 2.5/3D packaging for their specific design requirements. They will share highlights of the Samsung Chiplet Advanced Platform Engine (SCAPE) that provides customers with an innovative platform to realize the most optimal architecture in the context of performance and cost. Samsung will also share the collaboration work with Synopsys on 3DIC Compiler that maximizes the benefits of SCAPE by providing a comprehensive, integrated co-design and analysis solution to enable customers to achieve the targets with greater efficiency and faster time to production.
Michael Braun, Product Marketing for Semiconductor Test, Advantest
Overall design size and complexity combined with modern ATPG fault models leads to ever-increasing SCAN test data volumes on ATE. Test pattern run times grew from seconds to minutes per device, and conventional scan test access paths are part of the problem: A low-speed, GPIO-based parallel interface may not be sufficient anymore to transfer massive amounts of test data in a reasonable amount of time. In addition, SCAN test patterns are being deployed in System-Level Test (SLT) or even for regular ‘health checks’ of the device in the end application. To enable this, a standard interface like USB or PCIe must be used to transfer the test content, since the parallel test port used on ATE is typically not accessible. This paper presents how to enable SCAN test through functional HSIO on V93000 production ATE: A new type of digital instrument stores all the test data and connects to the device through a standard HSIO I/F using its native protocol. Synopsys High-Speed Access & Test (HSAT) IP inside the device drives the test data through the scan chains. Result evaluation and post-processing is done on the ATE instrument, supported by a TestMAX ALE embedded software component running locally on the tester. Using this new methodology enables a significant increase in the test content transfer rate on production ATE, using widely available and standardized high-speed interfaces with a relatively low pin count. This also enables the transfer of test content between different test insertions, like ATE and SLT, as well as the deployment of production test patterns for in-system test usage.
James Guan, Intel
As advanced process is getting more complex, high-quality diagnosis and defect identification becomes more challenging and time consuming. YE is a powerful tool to help failure analysis and yield engineers identify key yield killers and select FA samples quickly based on volume diagnostic analysis. This presentation demonstrates YE application in root causing scan and memory failures to improve advanced process yield.
Steve Crosher, Synopsys
Advanced node technologies underpin the capabilities offered by High Performance Computing. Challenges associated with the physical management of multi-core architectures within high gate density, large scale designs are well documented. Chip power consumption does not only require management but also requires optimizing in order to deploy competitive products and meet user experience expectations. The reduction of voltage supply throughout a chip is attractive, with any reduction saving dynamic power proportional to the square of the supply voltage with further potential static power savings due to lower die temperatures. The question is therefore, by how much can I reduce supply voltages whilst maintaining sufficient functionality and performance of embedded logic during operational mode?
The set-up and hold timing margins, or ‘slack’, of digital logic is sensitive to supply. Therefore, an opportunity is created to apply timing path monitors at multiple locations within a chip that support adaptive voltage scaling schemes for power optimization tailored to each individual device. Such monitoring should have a small area footprint and be non-intrusive, running in parallel to the functional mode of the device. In this session an overview will be provided of the current requirements of the chip design community, path margin monitor implementation and how such monitors sit within the wider scope of analytics applied to silicon lifecycle management.