DesignCon 2021

August 16 - 18
San Jose Convention Center

Why Attend

DesignCon is the premier high-speed communications and system design conference, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. At this year’s event, Synopsys features the DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions in Amphenol and Samtec booths, showing best performance at superior bit-error rate (BER). 

 

Synopsys IP Demos

Amphenol Booth #707

See Synopsys 112G Ethernet PHY IP loopback performance with long reach DAC achieving orders of magnitude better BER than the CEI-112G-LR specification, using Amphenol’s MCBs and OSFP cables

Samtec Booth #907

See Synopsys PCIe 6.0 and 112G Ethernet PHY IP performance with superior BER, using Samtec’s HSEC6 characterization board and APX6-RA connector board 

 

Panel

Monday, August 16
4:45 PM – 6:00 PM

Panel — PCIe 6.0: New Challenges & New Tests for an Old Standard 

This panel discussion focuses on several aspects of the PCIe 6.0 Design and verification. The panelists will discuss Signal Integrity Challenges, Crosstalk, Test and Measurement Challenges, with a deep dive about how to accurately measure SNDR with up to -dB of package loss plus break-out channel losses. In addition, the impact of SSC on SNDR measurement, how to accurately characterizing PCIe 6.0 transmitters, Simulation Challenges, Connector and cable requirements, use of retimers, as well as add-in card's requirements will be discussed. 

Synopsys Speakers:
Madhumita Sanyal, Sr. Technical Marketing Manager
Rita Horner, Sr. Technical Marketing Manager 

 

We look forward to seeing you at DesignCon