Cloud native EDA tools & pre-optimized hardware platforms
The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the design process and the eventual product. By maintaining a RISC-V ISA baseline, compatibility with and reuse of existing processor ecosystem elements is facilitated.
Synopsys ASIP Designer™ is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP. Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology, the ISA and microarchitecture can be tuned quickly to the application domain.
Please join us in the free-of-charge ASIP Designer Workshop on Monday, February 6, 2023. In this informal forum you will be able to exchange ideas, build up networks and gain first-hand insight about ASIP Designer directly from your peers.
This workshop will provide participants with more in-depth information, demonstrating the ASIP design methodology based on the ASIP Designer tools. Starting from an initial RISC-V architecture, we will demonstrate how to come to an application specific architecture, featuring instruction level and data level parallelism.
• Introduction to the ASIP Designer tool
• Learn about the steps to get to both the synthesizable RTL as well as a software development kit (SDK) including a C-compiler
• Learn about the wide range of architectural choices when designing a processor, enabling the design of a specialized controllers, DSPs, and programmable data paths
• Discuss architectural exploration capabilities of the ASIP Designer tools
• Discuss the ASIP implementation (RTL) and verification flow