Dineshkumar Selvaraj, Infineon Technologies AG and Kevin Brand, Senior R&D Engineer, Synopsys
In next-generation Infineon AURIX™ architectures, the ARC™ EV based Parallel Processing Unit (PPU) addresses the new performance requirements arising from e-Mobility, ADAS/AD, and new E/E architectures for increasingly connected vehicles. This session, through practical case studies, presents the benefits of engaging early with Virtual Prototyping (VP) for pre-silicon embedded software development within Infineon, from PPU software concept engineering studies through early driver development, integration and verification. The session gives an overview of the integrated VP technology and models, highlighting the VP through typical use cases in the automotive domain and through a PPU case study demo based on OpenCL. We show how such a pre- and post-silicon development platform accelerates software partners to enable the supply chain of the next generation AURIX device.
Chris Clark, Senior Manager, Automotive Group, Synopsys
It is clear that centralized computing for vehicles is around the corner and will play a major role in the world of automotive. In fact, we are already starting to see the first steps in this direction. Join me as we talk about the direction of Synopsys DesignWare ARC Processor automotive capabilities, digital twins, software testing, and ways to achieve reliable, safe, and secure software utilizing modern software development practices. Learn how having the ARC platform, supporting hardware and tool chain for the job is just one step towards the future software-defined vehicle.
Pieter Van Der Wolf, Principal R&D Engineer, Synopsys
The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/lidar – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams while preserving their software investment; it’s just not practical to start over when the current or next design requires a higher or lower level of throughput. This session will highlight some of the sensor fusion applications driving the need for more efficient digital signal processing and key ARC VPX DSP IP functions that can be optimized to handle a spectrum of sensor fusion workloads while adhering to a single programming environment.
Tom Michiels, Sr. R&D Engineer, Synopsys
Neural networks in embedded real-time applications have continued to evolve over the last 10 years. This presentation will consider the current state of the art for convolutional neural networks and introduce Transformer Neural Networks. Transformers are already considered a leading technology for natural language processing and other time series data applications. Transformer neural network architectures also are being applied to vision applications. Architecture and performance comparisons between transformers and CNNs will be covered.
Yaroslav Donskov, Sr Software Engineer, Synopsys
Natural Language Processing (NLP) is a type of artificial intelligence, which gives machines the ability to respond to text or voice. Natural Language Understanding (NLU) is a sub-topic of NLP, focused on understanding meaning. In this talk, we will show how we built a demonstrator which models a voice-controlled automotive navigation system, using modern, neural-network-based approaches to understand queries from the driver. We will describe how we used a Synopsys ARC VPX DSP Processor and an optimized NN kernel library to achieve high performance and accuracy on a resource-constrained embedded system.
Terry (Tai-Ling) Yeh, Engineer, ITRI
One challenge of developing an AI SoC is the need to simulate computational intensive algorithms like neural networks before the chip returns from the fab. Faced with a diversity of requirements, ITRI created a software development and debugging platform that provides a quick AI system design flow from software to RTL. This talk will discuss the advantages of using a virtual platform (Virtualizer) such as quick platform creation, quick software development and rich utilities for data tracking. It will also discuss how adding a hardware emulator (ZeBu) to create a hybrid emulation approach can provide accurate performance compare to Virtualizer model along and can perform RTL level performance bottleneck hunting.
Rich Collins, Director of Product Marketing, Synopsys
Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today, many embedded applications such as those found in artificial intelligence (AI), automotive and storage segments require the increased bandwidth and memory space advantages 64-bit processing can provide. As Moore’s law slows, design teams seek different ways to deliver unique solutions for these applications while maintaining power, performance, and area (PPA) goals. Designers commonly start with a standard ISA based processor to benefit from common tools, and software ecosystem, but look to extend the architecture to meet their product’s unique needs. This discussion will explore how highly extensible processor architectures can enable designers to meet their 64-bit application requirements and provide SoC differentiation.
Joachim Hampp, Product Architect, TASKING Germany GmbH
Increasingly, automotive SoCs are implementing heterogeneous multicore microcontrollers that consist of several identical processor cores, several different processors/controllers to perform specialized tasks, as well as parallel processing units to increase overall performance. However, there are a number of challenges to be addressed when switching from an embedded single core to a heterogeneous embedded multicore system. To avoid delays and unforeseen risks it is necessary to implement a highly optimized software architecture. Additionally, the software development and debug tools used must comprehensively support the selected heterogeneous multicore microcontroller and interact seamlessly with each other. Since the implementation of the software components typically takes place in phases over a potentially lengthy development period it is important to continuously focus on ensuring safety under the ISO 26262 or IEC 61508 standards for all software components and development tools. This presentation will describe these challenges and provide tips and techniques for addressing them.
Alexey Smirnov, Software Architect and Technical Lead, Synopsys
The rapidly increasing complexity of electronic functions in automobiles comes through the increased processing power of integrated circuits and the complexity of software running on those. In the post-Moore era, processing power is enabled by heterogeneous processing units. This trend requires application domain experts to become not only safety experts but also experts in programming specialized processors. This negatively affects the cost and time to market for new features. Model based development (MBD) appeared as a solution to meet the highest levels of safety requirements with less effort. Today, MBD also becomes a turnkey approach for cost efficient utilization of special purpose programmable hardware accelerators.
Watch the demos and interact with an expert
Building ASIL D Compliant SoCs with Synopsys’ Safety-Aware Solution & ARC FS Processor IP – Synopsys
With the global manufacturing chip constraints, first-time-right silicon has never been more important. Automotive SoC developers need first silicon to meet stringent ISO 26262 standards as well as power, performance and area targets. In this demo, we will showcase Synopsys’ Safety-Aware Solution, which includes tools and technology to reduce the risk of human error, accelerate the design cycle, and improve overall QoR. The Safety-Aware Solution for Random Hardware Faults allows designers to implement and verify functional safety mechanisms to address their ISO 26262 requirements. The demo uses ARC HS46FS Processor IP, showing how integrating ASIL D compliant processors simplifies the development of high-performance safety-critical applications to meet ISO 26262 certification.
Combining SLAM and Object Detection with DesignWare ARC EV Processor IP – Synopsys
Autonomous vehicles, robotics, augmented and virtual reality all require simultaneous localization and mapping (SLAM) to build a map of the surroundings. Combining SLAM with a neural network engine adds intelligence, allowing the system to identify objects and make decisions. In this demo, Synopsys ARC EV processor’s vision engine (VPU) accelerates KudanSLAM algorithms by up to 40% while running object detection on its CNN engine.
Fast & Accurate 3D Object Detection for LiDAR with DesignWare ARC EV Embedded Vision Processor IP – Synopsys
LiDAR is widely used in automotive ADAS applications because it can detect obstacles and the distance to each one. LiDAR processing has been traditionally done by DSPs, but now companies are applying the latest deep learning techniques to LiDAR object detection. This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on the ARC EV7x processor with DNN engine. The demo shows 3D boxes rendered onto objects detected in the video frames, enabling the development of safe and secure driver assistance systems.
Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP – Synopsys
This demo highlights building a CNN based application to recognize hand-written characters leveraging a Synopsys ARC EM processor and the embARC MLI library. Characters drawn on the screen will be passed to an EMNIST based neural network, which recognizes and displays the character on the screen along with the confidence value.
Moving Natural Language Processing to the Edge with DesignWare ARC VPX Processor IP –Synopsys
Smart speakers and voice-controlled devices are getting better at understanding our requests through natural language processing (NLP). Current NLP implementations handle the applications’ complex processing needs by sending requests to the cloud. To address the potential latency that is inherent in cloud processing, designers are integrating on-chip embedded processors to perform complex processing locally. This demonstration shows how Synopsys DesignWare® ARC® VPX DSP Processor IP can help move natural language processing from the cloud to embedded edge devices for lower latency with excellent power efficiency. ARC VPX DSP Processor IP is built on an advanced VLIW/SIMD architecture and optimized for high performance with low power consumption for always-on AI edge devices.
Real-time Trace: A Better Way to Debug Embedded Applications – Ashling
Ashling’s Ultra-XD is a high-performance real-time trace probe for embedded development and debug on Synopsys’ DesignWare ARC EM and HS processors. Developed in cooperation with Synopsys, the Ultra-XD probe integrates with the MetaWare Debugger and IDE (MDB and MIDE) under Windows or Linux based hosts. In this demo, Hugh O’Keeffe, Ashling VP of Global Engineering will show operation of the Ultra-XD with the Synopsys AXS103 Hardware Platform.
TASKING Tools for ARC Safety Critical Software – TASKING
See a demonstration of the upcoming TASKING SmartCode development environment supporting Synopsys ARC in automotive safety critical applications. This toolset contains dedicated C/C++ compilers and assemblers, a multi-core linker/locator and debugger all within a unified Eclipse™ Integrated Development Environment (IDE).
Vibrant Super Resolution (SR-GAN) with DesignWare ARC EV Processor IP – Synopsys
Super resolution constructs high-res images from low-res. Neural networks like SR-GAN can generate missing data to achieve impressive results. This demo shows SR-GAN running on ARC EV processor IP from Synopsys to generate beautiful images.