ARC Processor Virtual Summit 2021

Now available on demand

 

Why Attend?

Join us for the ARC® Processor Virtual Summit to hear our experts, users and ecosystem partners discuss the most recent trends and solutions that impact the development of SoCs for embedded applications.  This multi-day event will provide you with in-depth information from industry leaders on the latest ARC processor IP and related hardware/software technologies that enable you to achieve differentiation in your chip or system design.

Who Should Attend?

Whether you are a developer of chips, systems or software, the ARC Processor Virtual Summit will give you practical information to help you meet your unique performance, power and area requirements in the shortest amount of time.

Register Now

Get In-Depth Knowledge on the Latest Processor IP Trends

Automotive

Comprehensive solutions that help drive security, safety & reliability into automotive systems

AIoT

Power-efficient HW/SW solutions to implement a combination of artificial intelligence (AI) & internet of things (IoT) technologies in next-gen SoCs

Enabling Technologies

Solutions to accelerate SoC and software development to meet target performance, power and area requirements

Keynote Spotlight

Song Han

Assistant Professor at MIT’s EECS

Tuesday, September 21 | 9:15 a.m. PT

 

TinyML and Efficient Deep Learning

Today’s AI is too big. Deep neural networks demand extraordinary levels of data and computation, and therefore power, for training and inference. This severely limits the practical deployment of AI in edge devices. We aim to improve the efficiency of neural network design. First, I’ll present MCUNet that brings deep learning to IoT devices. MCUNet is a framework that jointly designs the efficient neural architecture (TinyNAS) and the light-weight inference engine (TinyEngine), enabling ImageNet-scale inference on micro-controllers that have only 1MB of Flash. Next I will introduce Once-for-All Network, an efficient neural architecture search approach, that can elastically grow and shrink the model capacity according to the target hardware resource and latency constraints. From inference to training, I’ll present TinyTL that enables tiny transfer learning on-device, reducing the memory footprint by 7-13x. Finally, I will describe data-efficient GAN training techniques that can generate photo-realistic images using only 100 images, which used to require tens of thousands of images. We hope such TinyML techniques can make AI greener, faster, more efficient and more sustainable.

 


 

From Assisted to Automated Driving

The development of assisted and automated driving technologies continue to advance at a rapid pace.  While the introduction of Level 5 autonomous vehicles capable of unsupervised driving in unstructured environments remains a long term goal, we are well on our way with Level 1 and 2 functions already available in many cars today. This keynote presentation will explore the challenges we face in achieving higher levels of automation, as well as the enabling technologies, new vehicle architectures and enhanced design methodologies that are necessary to deploy Level 3 and 4 automated systems.

Dr. Jürgen Bortolazzi

Head of Advanced Driver Assistance Systems and Automated Driving at Porsche AG

Wednesday, September 22 | 9:15 a.m. PT

Tracks Sessions


Day One: Tuesday, September 21

10:00 - 10:40 AM PT

Build Safe & Secure Automotive SoCs with ISO 26262 Compliant Security IP

Ruud Derwig, Senior Staff Engineer, Synopsys

The automotive industry is undergoing a significant transformation. Cars are offering increased connectivity and capabilities to provide a better driver/passenger experience. The increased connectivity means that they are also collecting and transmitting more sensitive data between in-car systems and the cloud, and thus are becoming very attractive targets to hackers. Security must be addressed from the ground up starting with the SoC, and when applied to cars, security needs to be approached together with automotive safety in a holistic manner. Designing security into automotive SoCs from the hardware level with safe and secure Hardware Secure Module (HSM) IP with a root of trust will help ensure that connected cars behave as expected, prevent random and systematic faults, and are able to fend off malicious attacks. Join this session to learn how the tRoot HSM for Automotive and ARC SEM130FS Processor implement the critical security and safety functions required throughout the automotive SoC life cycle.

11:20 - 12:00 PM PT

Understanding Classic and Adaptive AUTOSAR - Architecture, Benefits and Use Cases

Tarav Shah, Infrastructure Product Manager, Elektrobit

With shorter development cycles, software complexity and safety & security requirements facing the automotive industry, challenges exist to deliver system components to OEMs or Tier 1s to meet start of production (SOP) dates and provide updates or new features after SOP. AUTOSAR is the key to a centralized ECU architecture for mass production ready system components that are safe, secure and flexible. In this presentation we will map out vehicle and ECU architecture (including the Synopsys ARC Functional Safety Processor), benefits for both Classic and Adaptive AUTOSAR development and define best use case scenarios.

12:00 - 12:40 PM PT

New Embedded Model for Fast & Accurate 3D Object Detection for LiDAR

Selameab Demilew, Computer Vision Engineer, Sensor Cortek

Robust and timely perception of the environment is an essential requirement of all autonomous and semi-autonomous systems. This necessity has been the main factor behind the rapid growth and adoption of LiDAR sensors within the ADAS sensor suite. This presentation will describe a new, fast and accurate 3D object detector, FA3D, that converts raw point clouds collected by LiDARs into sparse occupancy cuboids to detect cars and other road agents using a deep convolutional neural network. This highly flexible mode uses an efficient input encoding representation that is multiple times faster to compute on a CPU and more compact to transfer to a GPU, without increasing power. As a result, FA3D reduces by almost 50% the detection runtime compared to popular 3D detection networks and performs on par with other state-of-the-art models. The performance results of this network will be demonstrated for the case of vehicle and vulnerable road user detection. The presentation will also compare the performance of this model on three off-the-shelf neural network accelerators: 1) a high-end workstation equipped with a Core-i7 CPU and a RTX 2080 Ti graphics card, 2) a Jetson AGX Xavier (a single board embedded computer with an 8-core ARM processor and 512-core Volta GPU), and 3) Synopsys DesignWare EV Vision Processor IP core with a highly optimized CNN engine.

AIoT + -

10:00 - 10:40 AM PT

Real World AI: Applying Vision and Deep Learning to make Electric Carts Safer

Dor Zepeniuk , CTO & VP Products, Inuitive

Artificial Intelligence continues to find ways to improve the world around us. Working with their partner Alps Alpine, Inuitive discusses how they applied expertise in system design, computer vision and deep Learning/AI to make electric carts safer. This talk will discuss the challenges in the design including overcoming environmental, safety, performance and cost issues. Also discussed will be the need and process for retraining off the shelf neural networks and how combining depth sensing with neural networks can provide the optimum solution.

11:20 - 12:00 PM PT

How SiMa.ai Addresses Security at the Edge with Comprehensive Hardware and IP Solutions

Sharath Raghava, System Architect, SiMa.ai

With the evolution of edge computing, edge devices are handling more data processing at the source instead of sending it to the cloud. The edge devices are distributed and decentralized, enabling them to perform necessary computations on-device rather than outsourcing it to the cloud. These devices report results into aggregators and eventually into a centralized compute resource on the premises or cloud. This heterogeneous architecture offers some data security advantages but also brings increased risks in access security. Join this session with SiMa.ai to learn how SiMa.ai is addressing security risks at the edge by providing comprehensive solutions within its leading MLSoC™ platform including the root of trust, secure boot, and runtime authentication to address diverse customer needs. SiMa.ai will also describe their driving factors for integrating security IP for target applications such as automotive, autonomous, robotics and computer vision.

12:00 - 12:40 PM PT

Addressing IoT Communications Requirements with an Ultra-Low Power NB-IoT Subsystem Solution

Omar Cruz, Product Marketing Manager, Synopsys

NB-IoT technology has been designed to significantly reduce the power consumption of communication devices and improve spectrum efficiency. Demand for greater design complexity and extended coverage for ultra-low power IoT applications has driven a worldwide proliferation in wireless technology with NB-IoT protocol support. This presentation highlights the key challenges and requirements of today’s NB-IoT modem designs and gives an overview of the Synopsys DesignWare ARC IoT Communications IP Subsystem, which leverages the efficiency and extensibility of the ARC EM11D processor with integrated, pre-verified hardware and software IP to help shorten the time-to-market for developing IoT communication products.

10:00 - 10:40 AM PT

Optimizing SoC Simulation Time by >5X Using an Instruction Accurate Behavioral Model Provided by Synopsys DesignWare® ARC® nSIM

Ravi Mangal, Manager, ASIC Design Verification, Micron

A typical SoC has multiple processors to offload the main CPU and achieve the required bandwidth for data intensive end-to-end operations. Verification of these SoCs requires compiling C code and loading this compiled code into the processor, after which the CPU starts executing these instructions and initiates a series of read/write operations on the system bus. Since processors are mostly pre-verified, the verification at the SoC level is mostly targeted to check interactions among multiple peripherals and memories. A datapath scenario is time consuming because of the large number of memory read, write and compare operations and reproducing a failure might cause a lot of rerun time due to long running memory accesses. To overcome this issue, most of the SoC level environment performs backdoor operations on memory access but this requires modifications in the C tests along with handshaking with the SV/UVM testbench. The same C test cannot be run on FPGA/emulation platforms due to backdoor dependencies, which creates issues with reusability of C tests on these platforms. In this presentation, we will describe how integrating the Synopsys ARC nSIM instruction set simulator in our simulation environment reduced simulation runtime by more than 5x.

11:20 - 12:00 PM PT

Software Self-Test as a Safety Mechanism for Processing Units

Nikolay Anikeev, Software Architect and Technical Lead, Synopsys

The growing dependency of modern automobiles on electronic functions increases the need for many kinds of integrated circuits (IC) for safety critical applications. Requirements coming from different in-car subsystems mandate chip manufactures to create a wide range of specialized solutions. This in turn raises the bar for automotive IP suppliers and pushes them to offer configurable and extensible IP products. When IP configurability meets safety standards, it brings new technical challenges. Dual core lock step (DCLS), which is now the dominating safety mechanism for processing units, cannot work anymore as a one-fits-all approach. Increasing complexity of automotive grade ICs requires non-DCLS solutions. This trend brings new safety mechanisms into play. Software based self-test is one of those which has started to see increased demand. This presentation introduces Software Test Libraries (or STL) and explains how a holistic safety approach to hardware design can help to create an optimal combination of hardware and software safety mechanisms, demonstrating the best possible power, performance, area hardware metrics and minimal runtime software overheads.

12:00 - 12:40 PM PT

Design for ADAS and Autonomous Driving SoC Using ARC Processor IP and Synopsys’ Safety-Aware Solution to Achieve ASIL D Random Hardware Metrics

Shiv Chonnad, Sr. Staff Functional Safety Engineer, Synopsys

With the rapid shift to ADAS and autonomous driving, carmakers are transitioning to a more centralized domain architecture with central compute. The system-on-chip (SoC) manages every aspect of its domain while at the same time ensuring safe and secure operation. Complex automotive SoCs require automotive-grade IP and ISO 26262-certified safety-aware test, design implementation, and verification solutions for hardware and software elements of the SoC to meet the strictest functional safety objectives while achieving power-performance-area (PPA) targets. This session provides an overview of automotive trends, describes Synopsys’ safety-aware solution to enable and accelerate ASIL-compliant SoC designs, and delivers a video demonstration of an ARC HS46FS processor IP analyzed, implemented and verified using Synopsys’ safety-aware solution to achieve ASIL D random hardware metrics.

10:40 - 11:20 AM PT

Live Demos

Watch the demos and interact with an expert

Building ASIL D Compliant SoCs with Synopsys’ Safety-Aware Solution & ARC FS Processor IP – Synopsys

With the global manufacturing chip constraints, first-time-right silicon has never been more important. Automotive SoC developers need first silicon to meet stringent ISO 26262 standards as well as power, performance and area targets. In this demo, we will showcase Synopsys’ Safety-Aware Solution, which includes tools and technology to reduce the risk of human error, accelerate the design cycle, and improve overall QoR. The Safety-Aware Solution for Random Hardware Faults allows designers to implement and verify functional safety mechanisms to address their ISO 26262 requirements. The demo uses ARC HS46FS Processor IP, showing how integrating ASIL D compliant processors simplifies the development of high-performance safety-critical applications to meet ISO 26262 certification.

Combining SLAM and Object Detection with DesignWare ARC EV Processor IP – Synopsys

Autonomous vehicles, robotics, augmented and virtual reality all require simultaneous localization and mapping (SLAM) to build a map of the surroundings. Combining SLAM with a neural network engine adds intelligence, allowing the system to identify objects and make decisions. In this demo, Synopsys ARC EV processor’s vision engine (VPU) accelerates KudanSLAM algorithms by up to 40% while running object detection on its CNN engine.

Fast & Accurate 3D Object Detection for LiDAR with DesignWare ARC EV Embedded Vision Processor IP – Synopsys

LiDAR is widely used in automotive ADAS applications because it can detect obstacles and the distance to each one. LiDAR processing has been traditionally done by DSPs, but now companies are applying the latest deep learning techniques to LiDAR object detection. This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on the ARC EV7x processor with DNN engine. The demo shows 3D boxes rendered onto objects detected in the video frames, enabling the development of safe and secure driver assistance systems.

Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP – Synopsys

This demo highlights building a CNN based application to recognize hand-written characters leveraging a Synopsys ARC EM processor and the embARC MLI library. Characters drawn on the screen will be passed to an EMNIST based neural network, which recognizes and displays the character on the screen along with the confidence value.

Moving Natural Language Processing to the Edge with DesignWare ARC VPX Processor IP –Synopsys

Smart speakers and voice-controlled devices are getting better at understanding our requests through natural language processing (NLP). Current NLP implementations handle the applications’ complex processing needs by sending requests to the cloud. To address the potential latency that is inherent in cloud processing, designers are integrating on-chip embedded processors to perform complex processing locally. This demonstration shows how Synopsys DesignWare® ARC® VPX DSP Processor IP can help move natural language processing from the cloud to embedded edge devices for lower latency with excellent power efficiency. ARC VPX DSP Processor IP is built on an advanced VLIW/SIMD architecture and optimized for high performance with low power consumption for always-on AI edge devices.

Real-time Trace: A Better Way to Debug Embedded Applications – Ashling

Ashling’s Ultra-XD is a high-performance real-time trace probe for embedded development and debug on Synopsys’ DesignWare ARC EM and HS processors. Developed in cooperation with Synopsys, the Ultra-XD probe integrates with the MetaWare Debugger and IDE (MDB and MIDE) under Windows or Linux based hosts. In this demo, Hugh O’Keeffe, Ashling VP of Global Engineering will show operation of the Ultra-XD with the Synopsys AXS103 Hardware Platform.

TASKING Tools for ARC Safety Critical Software – TASKING

See a demonstration of the upcoming TASKING SmartCode development environment supporting Synopsys ARC in automotive safety critical applications. This toolset contains dedicated C/C++ compilers and assemblers, a multi-core linker/locator and debugger all within a unified Eclipse™ Integrated Development Environment (IDE).

Vibrant Super Resolution (SR-GAN) with DesignWare ARC EV Processor IP – Synopsys

Super resolution constructs high-res images from low-res. Neural networks like SR-GAN can generate missing data to achieve impressive results. This demo shows SR-GAN running on ARC EV processor IP from Synopsys to generate beautiful images.

Day Two: Wednesday, September 22

10:00 - 10:40 AM PT

Accelerate ARC Automotive Software Development with Next Gen Infineon AURIX™ Virtual Prototypes

Dineshkumar Selvaraj, Infineon Technologies AG and Kevin Brand, Senior R&D Engineer, Synopsys

In next-generation Infineon AURIX™ architectures, the ARC™ EV based Parallel Processing Unit (PPU) addresses the new performance requirements arising from e-Mobility, ADAS/AD, and new E/E architectures for increasingly connected vehicles. This session, through practical case studies, presents the benefits of engaging early with Virtual Prototyping (VP) for pre-silicon embedded software development within Infineon, from PPU software concept engineering studies through early driver development, integration and verification. The session gives an overview of the integrated VP technology and models, highlighting the VP through typical use cases in the automotive domain and through a PPU case study demo based on OpenCL. We show how such a pre- and post-silicon development platform accelerates software partners to enable the supply chain of the next generation AURIX device.

10:40 - 11:20 AM PT

Software-Defined Vehicles: Why Having the Right Hardware Is Just the Start

Chris Clark, Senior Manager, Automotive Group, Synopsys

It is clear that centralized computing for vehicles is around the corner and will play a major role in the world of automotive. In fact, we are already starting to see the first steps in this direction. Join me as we talk about the direction of Synopsys DesignWare ARC Processor automotive capabilities, digital twins, software testing, and ways to achieve reliable, safe, and secure software utilizing modern software development practices. Learn how having the ARC platform, supporting hardware and tool chain for the job is just one step towards the future software-defined vehicle.

12:00 - 12:40 PM PT

DSP IP for Implementing High Performance Sensor Fusion on an Embedded Budget

Pieter Van Der Wolf, Principal R&D Engineer, Synopsys

The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/lidar – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams while preserving their software investment; it’s just not practical to start over when the current or next design requires a higher or lower level of throughput. This session will highlight some of the sensor fusion applications driving the need for more efficient digital signal processing and key ARC VPX DSP IP functions that can be optimized to handle a spectrum of sensor fusion workloads while adhering to a single programming environment.

AIoT + -

10:00 - 10:40 AM PT

What’s Next for Neural Networks: Will Transformer Neural Networks Replace RNNs and CNNs?

Tom Michiels, Sr. R&D Engineer, Synopsys

Neural networks in embedded real-time applications have continued to evolve over the last 10 years. This presentation will consider the current state of the art for convolutional neural networks and introduce Transformer Neural Networks. Transformers are already considered a leading technology for natural language processing and other time series data applications. Transformer neural network architectures also are being applied to vision applications. Architecture and performance comparisons between transformers and CNNs will be covered.

10:40 - 11:20 AM PT

High-Performance Natural Language Processing in Constrained Embedded Systems

Yaroslav Donskov, Sr Software Engineer, Synopsys

Natural Language Processing (NLP) is a type of artificial intelligence, which gives machines the ability to respond to text or voice. Natural Language Understanding (NLU) is a sub-topic of NLP, focused on understanding meaning. In this talk, we will show how we built a demonstrator which models a voice-controlled automotive navigation system, using modern, neural-network-based approaches to understand queries from the driver. We will describe how we used a Synopsys ARC VPX DSP Processor and an optimized NN kernel library to achieve high performance and accuracy on a resource-constrained embedded system.

12:00 - 12:40 PM PT

A Hybrid Platform for Software Development on an AI SoC

Terry (Tai-Ling) Yeh, Engineer, ITRI

One challenge of developing an AI SoC is the need to simulate computational intensive algorithms like neural networks before the chip returns from the fab. Faced with a diversity of requirements, ITRI created a software development and debugging platform that provides a quick AI system design flow from software to RTL. This talk will discuss the advantages of using a virtual platform (Virtualizer) such as quick platform creation, quick software development and rich utilities for data tracking. It will also discuss how adding a hardware emulator (ZeBu) to create a hybrid emulation approach can provide accurate performance compare to Virtualizer model along and can perform RTL level performance bottleneck hunting.

10:00 - 10:40 AM PT

64-bit Applications Get a Helping Hand: Extensible Processor Architecture

Rich Collins, Director of Product Marketing, Synopsys

Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today, many embedded applications such as those found in artificial intelligence (AI), automotive and storage segments require the increased bandwidth and memory space advantages 64-bit processing can provide. As Moore’s law slows, design teams seek different ways to deliver unique solutions for these applications while maintaining power, performance, and area (PPA) goals. Designers commonly start with a standard ISA based processor to benefit from common tools, and software ecosystem, but look to extend the architecture to meet their product’s unique needs. This discussion will explore how highly extensible processor architectures can enable designers to meet their 64-bit application requirements and provide SoC differentiation.

10:40 - 11:20 AM PT

Software Development for Safety-Critical Heterogeneous Multicore MCUs with Parallel Processing Unit

Joachim Hampp, Product Architect, TASKING Germany GmbH

Increasingly, automotive SoCs are implementing heterogeneous multicore microcontrollers that consist of several identical processor cores, several different processors/controllers to perform specialized tasks, as well as parallel processing units to increase overall performance. However, there are a number of challenges to be addressed when switching from an embedded single core to a heterogeneous embedded multicore system. To avoid delays and unforeseen risks it is necessary to implement a highly optimized software architecture. Additionally, the software development and debug tools used must comprehensively support the selected heterogeneous multicore microcontroller and interact seamlessly with each other. Since the implementation of the software components typically takes place in phases over a potentially lengthy development period it is important to continuously focus on ensuring safety under the ISO 26262 or IEC 61508 standards for all software components and development tools. This presentation will describe these challenges and provide tips and techniques for addressing them.

12:00 - 12:40 PM PT

Model Based Development for ARC Processor IP

Alexey Smirnov, Software Architect and Technical Lead, Synopsys

The rapidly increasing complexity of electronic functions in automobiles comes through the increased processing power of integrated circuits and the complexity of software running on those. In the post-Moore era, processing power is enabled by heterogeneous processing units. This trend requires application domain experts to become not only safety experts but also experts in programming specialized processors. This negatively affects the cost and time to market for new features. Model based development (MBD) appeared as a solution to meet the highest levels of safety requirements with less effort. Today, MBD also becomes a turnkey approach for cost efficient utilization of special purpose programmable hardware accelerators.

11:20 - 12:00 PM PT

Live Demos

Watch the demos and interact with an expert

Building ASIL D Compliant SoCs with Synopsys’ Safety-Aware Solution & ARC FS Processor IP – Synopsys

With the global manufacturing chip constraints, first-time-right silicon has never been more important. Automotive SoC developers need first silicon to meet stringent ISO 26262 standards as well as power, performance and area targets. In this demo, we will showcase Synopsys’ Safety-Aware Solution, which includes tools and technology to reduce the risk of human error, accelerate the design cycle, and improve overall QoR. The Safety-Aware Solution for Random Hardware Faults allows designers to implement and verify functional safety mechanisms to address their ISO 26262 requirements. The demo uses ARC HS46FS Processor IP, showing how integrating ASIL D compliant processors simplifies the development of high-performance safety-critical applications to meet ISO 26262 certification.

Combining SLAM and Object Detection with DesignWare ARC EV Processor IP – Synopsys

Autonomous vehicles, robotics, augmented and virtual reality all require simultaneous localization and mapping (SLAM) to build a map of the surroundings. Combining SLAM with a neural network engine adds intelligence, allowing the system to identify objects and make decisions. In this demo, Synopsys ARC EV processor’s vision engine (VPU) accelerates KudanSLAM algorithms by up to 40% while running object detection on its CNN engine.

Fast & Accurate 3D Object Detection for LiDAR with DesignWare ARC EV Embedded Vision Processor IP – Synopsys

LiDAR is widely used in automotive ADAS applications because it can detect obstacles and the distance to each one. LiDAR processing has been traditionally done by DSPs, but now companies are applying the latest deep learning techniques to LiDAR object detection. This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on the ARC EV7x processor with DNN engine. The demo shows 3D boxes rendered onto objects detected in the video frames, enabling the development of safe and secure driver assistance systems.

Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP – Synopsys

This demo highlights building a CNN based application to recognize hand-written characters leveraging a Synopsys ARC EM processor and the embARC MLI library. Characters drawn on the screen will be passed to an EMNIST based neural network, which recognizes and displays the character on the screen along with the confidence value.

Moving Natural Language Processing to the Edge with DesignWare ARC VPX Processor IP –Synopsys

Smart speakers and voice-controlled devices are getting better at understanding our requests through natural language processing (NLP). Current NLP implementations handle the applications’ complex processing needs by sending requests to the cloud. To address the potential latency that is inherent in cloud processing, designers are integrating on-chip embedded processors to perform complex processing locally. This demonstration shows how Synopsys DesignWare® ARC® VPX DSP Processor IP can help move natural language processing from the cloud to embedded edge devices for lower latency with excellent power efficiency. ARC VPX DSP Processor IP is built on an advanced VLIW/SIMD architecture and optimized for high performance with low power consumption for always-on AI edge devices.

Real-time Trace: A Better Way to Debug Embedded Applications – Ashling

Ashling’s Ultra-XD is a high-performance real-time trace probe for embedded development and debug on Synopsys’ DesignWare ARC EM and HS processors. Developed in cooperation with Synopsys, the Ultra-XD probe integrates with the MetaWare Debugger and IDE (MDB and MIDE) under Windows or Linux based hosts. In this demo, Hugh O’Keeffe, Ashling VP of Global Engineering will show operation of the Ultra-XD with the Synopsys AXS103 Hardware Platform.

TASKING Tools for ARC Safety Critical Software – TASKING

See a demonstration of the upcoming TASKING SmartCode development environment supporting Synopsys ARC in automotive safety critical applications. This toolset contains dedicated C/C++ compilers and assemblers, a multi-core linker/locator and debugger all within a unified Eclipse™ Integrated Development Environment (IDE).

Vibrant Super Resolution (SR-GAN) with DesignWare ARC EV Processor IP – Synopsys

Super resolution constructs high-res images from low-res. Neural networks like SR-GAN can generate missing data to achieve impressive results. This demo shows SR-GAN running on ARC EV processor IP from Synopsys to generate beautiful images.

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