Why Attend?

Join Synopsys at this year’s AI Hardware Summit, the predominant leadership forum for AI hardware. As a partner to the world's most innovative companies, Synopsys has worked alongside many AI pioneers to enable the creation of the world's most advanced AI "super chips". Synopsys provides powerful enablement solutions such as reference flows, AI-focused design and verification tools, expert design services, and the industry's most comprehensive IP portfolio to meet the needs of AI SoCs. Don’t miss the Keynote, "Enter the Era of Autonomous Design: Personalizing Chips for 1,000X More Powerful AI Compute", from Synopsys' President and Chief Operating Officer, Sassine Ghazi.

Synopsys Presence

Featured Keynote

Wednesday, September 14 | 6:00 p.m. PDT

Enter the Era of Autonomous Design: Personalizing Chips for 1,000X More Powerful AI Compute

 

Sassine Ghazi

President and Chief Operating Officer

Macrotrends in innovation are leveraging both software and chips to create the next round of world-changing products. Unlocking the vast potential offered by this innovation model is daunting however. Systemic complexity across all disciplines from silicon to software must be addressed in a holistic way to achieve success. AI applications change over months while chip design can take years, adding to the challenges. Talent shortages also create headwinds. And as more system companies engage in chip design, these headwinds can have a profound impact on the pace of innovation.

Complex chip and system design must be easier to achieve in less time. Sassine Ghazi will discuss several developing strategies that use AI and machine learning techniques to dramatically reduce design time and design risk, opening the opportunity for substantial increases in the pace of innovation.

Technical Presentation

Thursday, September 15 | 11:10 a.m. PDT

Hardware & Systems: Will your Next AI Processor Design Itself? Real-World Case Studies in Autonomous Design

Stelios Diamantidis

Senior Director & Head of Autonomous Design Solutions, Synopsys

Approximately one year ago, Samsung confirmed the world’s first use of AI to design a mobile processor chip. Since then, AI-driven design has been adopted across the industry at a phenomenal pace, accelerating silicon innovations to market in automotive, high-performance computing, consumer electronics, and other applications. Will this pace of innovation ultimately lead to self-designed silicon? In this sequel to the Day-1 Keynote – Enter the Era of Autonomous Design: Personalizing Chips for 1,000X More Powerful AI Compute, we will be looking at real-world examples of using AI to design chips, and reporting on the industry’s path to autonomous design. 

Panel Discussion at Edge Summit 2022

Wednesday, September 14 | 1:50 p.m. PDT

Co-design and co-optimization: maximizing energy per joule

Achieving full optimization requires co-design and co-optimization of AI algorithms and the hardware platforms where they will be executed. This panel will explore the benefits and potential of such co-design approaches.

Godwin Maben

Strategy & System Architects, Synopsys Fellow

Subutai Ahmad

VP of Research, Numenta

Anshumali Shrivastava

CEO and Founder, ThirdAI

Technical Workshop

Tuesday, September 13 | 9:00 a.m. PDT

Embracing the Power of Formal Methods to Enable Continuous Integration/Continuous Delivery of AI Processors 

Graphcore's Intelligence Processing Unit (IPU), built on its unique wafer-on-wafer technology architecture, enables innovators across all industries to undertake breakthrough research with the power of AI compute. To deliver what Graphcore believes will be the standard for machine intelligence compute, it follows a continuous integration (CI) and continuous delivery (CD) process to ensure incremental code changes are delivered quickly and reliably to production. In this workshop, Graphcore will share how it is using Synopsys formal verification solutions throughout the CI/CD process to deliver bug-free silicon.  Workshop topics include:

  •  An introduction to Sequential Equivalence Checking (SEQ) and Formal Testbench Analyzer (FTA) applications, part of Synopsys VC Formal
  • Graphcore’s formal verification deployment to maximize engineering productivity
  • How formal is modified for CI and CD
  • Strategies Graphcore employed to overcome reproducibility challenges at the CI stage

Manish Pandey

VP R&D, Synopsys Fellow

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