AI Hardware Summit US 2021

September 13-16
Hybrid Experience

Why Attend?

Join Synopsys at this year’s AI Hardware Summit, the predominant leadership forum for AI hardware. As a partner to the world's most innovative companies, Synopsys has worked alongside many AI pioneers to enable the creation of the world's most advanced AI "super chips" with powerful enablement solutions, including reference flows, AI-focused design and verification tools, expert design services, and the industry's most comprehensive AI-ready DesignWare IP portfolio. Don’t miss the Keynote, "Can AI Design AI Chips?", from Synopsys' Chairman and co-Chief Executive Officer, Dr. Aart de Geus.

Synopsys Presence

Featured Keynote

Tuesday, September 14 | 8:55 a.m. PDT

Builders of the Imaginary: From Artificial Intelligence to Artificial Architects in the Era of SysMoore

As we are propelled into an era of exponential, cloud-to-edge intelligence, it’s clear that emerging AI architectures will be born of a techonomic pull from a wide range of traditional and emerging marketing verticals. Synopsys Founder and co-CEO Aart de Geus will showcase new innovations set to empower architects and transform both architecture and artificial intelligence.

Dr. Aart de Geus

Chairman and co-Chief Executive Officer, Synopsys

Panel Discussion

Wednesday, September 15 | 4:15 p.m. PDT

From App to Silicon: Personalizing AI Hardware

AI model complexity is doubling every few months. With trillion+ parameter models already in hand, is AI hardware development keeping up with the intricacies of new AI applications? What would it take for system innovators to build and deploy custom silicon solutions in weeks instead of, currently, 18 months or longer? Our expert panel will look at the fascinating journey from cloud graphs to silicon and debate the future of application-specific cognitive systems.

Stelios Diamantidis

Senior Director, Artificial Intelligence Solutions, Synopsys

Karl Freund

Founder & Principal Analyst, Cambrian AI

Steve Oberlin

CTO, Accelerated Computing, NVIDIA

Technical Workshop

Monday, September 13 | 2:00 p.m. PDT

How Cerebras Does It: Building the Largest Chip Ever Made, and Delivering Unprecedented Deep Learning Acceleration

Can a wafer-sized SoC outperform some of the fastest supercomputers? If it’s from Cerebras Systems, the answer is YES. Cerebras’ innovative solution, based on the second generation Wafer Scale Engine, provides performance that next-generation ML researchers need to operate at a scale and speed never before thought possible.  This is changing the future of AI work as these researchers are enabled to develop new neural network architectures and algorithms that are neither efficient nor practical on existing infrastructure. In this workshop, Cerebras will reveal the systemic complexity challenges around compute, memory, and bandwidth when designing an AI chip of this scale, and how they overcome them with Synopsys’ AI design solutions, focusing on DesignWare IP, Verification, Digital Design, and Silicon Lifecycle Management.

Thomas Andersen

VP Engineering, Synopsys

Dhiraj Mallick

VP Engineering and Business Development, Cerebras

Virtual Live Panel

Hosted by Intel

Monday, September 13 | 12:10 p.m. PDT

Designing AI Super-Chips at the Speed of Memory

Hardware design has become a core enabler of innovation for the age of AI. Comprehensive design solutions are behind many AI "super-chips" and they’re pushing storage infrastructure beyond its limits. New approaches to addressing the system memory challenge for AI are being proposed that help designers cost-effectively configure more memory capacity, load data 1,000x faster than SSD, instantly rollback chip designs to a previous snapshot, or recover from a crash in a few seconds using the same in-memory snapshots. Panelists from Intel, MemVerge, and Synopsys will review the state of the industry to design super scale chips with systematic complexity in the post-Moore era and the memory walls the industry is facing, and discuss the benefits of persistent memory and virtualization including the commercial solutions available today.

Steve Scargall

Sr. Software Architect, Intel

Charles Fan

CEO & Co Founder, Memverge

Brandon Wang

VP, Corporate Strategic Programs & New Ventures, Synopsys

Technical Presentation

Monday, September 13 | 4:10 p.m. PDT

Shift-left Architecture Design for the Data-Driven Era

Designing SoC architectures for the era of data-driven AI applications is a very challenging task. Especially at the macro-architecture level, it involves combining heterogenous processing elements to achieve the optimal computational efficiency for the target AI workloads and optimizing the interconnect and memory architecture for the processing of huge data sets. Static analytical models are traditionally used to make high-level architecture design decisions, but for AI designs, these decisions can only be validated very late, when stable RTL and the complete software flow are available.

This session presents a flow for early architecture simulation of AI architectures to “shift left” the quantitative analysis by 6-12 months. Closing the large gap between analytical models and RTL based methods, architecture simulation accurately predicts performance and power using AI workload models and transaction-level hardware models, enabling design decisions based on systematic trade-off analysis, thus avoiding late and expensive changes to the SoC architecture. 

Tim Kogel

Principle Engineer for Virtual Prototyping, Synopsys

Demo: PCIe 6.0 IP, Connector and Cable Systems for AI Hardware Designs

This demo, in the Samtec booth, features Synopsys silicon-proven DesignWare PHY IP for PCIe 6.0, available in 7nm and 5nm processes, with Samtec connectors in a configurable, GPU-based AI/ML system. The demo shows high-performance at 64GT/s with maximum channel loss, using the Synopsys IP and Samtec's cable mesh and rigid-style backplane, high-speed edge card connectors, and precision RF interconnects.

Sponsored Roundtable

Thursday, September 16 | 10:00 a.m. PDT

How Far Can One Apply AI in Chip Design?

What would it take for system innovators to build and deploy custom silicon solutions in weeks instead of months to years? This roundtable explores what system design applications may be best suited for artificial intelligence assistants, and how a new generation of personalized chip solution could unlock opportunities in the broader AI space.

Thomas Andersen

VP Engineering, Synopsys

Stelios Diamantidis

Senior Director, Artificial Intelligence Solutions, Synopsys

Pre-Event Webinar

Optimized SoC Hardware for Highly Efficient AI Systems

Watch On-Demand Now

Forward-looking system and SoC architects are asking themselves: “What does the next generation of AI need?” Innovative companies are adopting approaches that offer flexible, future-proof adoption of new neural network models to function effectively on purpose-built ML devices. As tasks move from the cloud to the edge, each type of application requires workload-specific optimization of processing, memories, data movement, and security.

Join this webinar with Synopsys and to learn:

  • The emerging requirements of next-generation Cloud, Edge/Cloud, and Edge-Device SoCs and systems
  • Tradeoffs of hardware optimization – flexibility, power, throughput, and more
  •’s driving factors as they developed their low-power ML SoC for machine learning at the edge

Ron Lowman

AI Strategic Marketing Manager, Synopsys

Kavitha Prasad

VP, Business Development and Systems Applications,

Event Details

Hybrid Event - Virtual & In-Person


Virtual - September 13-16

In-Person - September 14-15
Computer History Museum, Mountain View, CA


3 Days of Live Content:

Day Zero: September 13 | 9:00 a.m. - 3:00 p.m. PDT

Day One: September 14 | 8:30 a.m. - 6:00 p.m. PDT

Day Two: September 15 | 8:55 a.m. - 6:00 p.m. PDT


Virtual Live Panel

September 13, 2021 | 12:10 - 12:50 p.m. PDT


Technical Workshop

September 13, 2021 | 2:00 - 3:00 p.m. PDT


Technical Presentation

September 13, 2021 | 4:10 - 4:35 p.m. PDT


Featured Keynote

September 14, 2021 | 8:55 - 9:30 a.m. PDT


Panel Discussion

September 15, 2021 | 4:15 - 4:55 p.m. PDT


Sponsored Roundtable

September 16, 2021 | 10:00 - 11:00 a.m. PDT

Synopsys is proud to be a Headline Partner at AI Hardware Summit

Use code SYNOPSYS10 to save 10%

Join us at AI Hardware Summit 2021