Synopsys Technology Digital Event

If you missed the recent Synopsys Technology Symposium series of seminars, please join us for this follow on webinar to catch the latest updates of analog/RF and digital design. You will see several date options below and you can register to one or both of the webinars.

Wednesday, October 26

Duration: 60 minutes


Thursday, November 3

Duration: 60 minutes


Thursday, November 10

Duration: 60 minutes


Analog and RFIC Design using Synopsys and Keysight Integrated Solution

The Analog/RF design session covers front-to-back IC design and verification using Synopsys Custom Design Family. Synopsys Custom Design Family accelerates the development of robust analog & mixed-signal design and RF designs spanning the frequency range of sub-6GHz to millimeter waves using Synopsys Custom Design Family, with integration of Keysight Pathwave RFIC Design (GoldenGate) for RF simulation and Pathwave RFPro for electromagnetic (EM) analysis. The session is joined by CoreHW, leading fabless semiconductor company providing design services, intellectual property (IP) to present their experiences with the flow.


Digital Design

Digital Design session will cover the Synopsys solution from comprehensive IP portfolio to high-end RTL to GDSII design and advanced verification - in emerging and established process nodes and various application domains such as automotive, high-performance computing and IoT. The session captures an overview of newest implementation and verification solutions such Synopsys award winning DSO.ai to autonomously explore the chip design solution space, RTL Architect to reduce development cycle and improve QoR, DesignDash for big data analytics driven design, 3DIC, Silicon Lifecycle Management and ML/AI enabled digital verification and design debug.