DesignWare OTP ULP IP

DesignWare One-Time Programmable (OTP) ULP Non-Volatile Memory (NVM) IP is designed to minimize active and standby power consumption, with standby power less than 0.25µA. The IP is available in several configurations ranging from 16 bits to 2 Kbits, and multiple macros can be combined to meet larger memory requirements. DesignWare ULP IP is designed to be low-power, field-programmable replacements for eFuses in applications such as precision analog trimming in automotive, medical, wireless and other systems.

Power for the ULP IP may be done with an external voltage source or with an optional power supply macro that supplies the programming and read voltages from a single VCC supply. The required read voltage is a very low 1.5V, and programming current requirements are much smaller than those needed for programming eFuses. The default read mode of the macro - differential/redundant - provides the highest level of chip security and reliability. ULP data is available at chip start-up.

ULP macros can be converted into mask-programmable ROMs with a single mask change. The user has the flexibility to mask program the entire memory or individual portions of the macrocell. This feature gives the customer the ability to mask program a section of the memory while allowing other sections of the memory to be programmed in the field.

Uses for ULP IP include:

DesignWare NVM IP Complete Solution
DesignWare One-Time Programmable ULP Non-Volatile Memory IP

 

Highlights
  • OTP Features
    • Retention exceeding 10 years (100% duty cycle)
    • Standard CMOS process
    • Highly secure
    • Ultra-low power consumption
    • Fast read access
    • Multiple read modes
    • Flexible Mask ROM option
  • ULP Features
    • Standard CMOS Logic Process
    • 1.8V core, 3.3V IO voltage
    • Up to 2 Kbits per macrocell
    • Multiple macrocells can be combined for larger OTP sizes
    • Up to 128 IO bits per macrocell
    • Optional Integrated Power Supply (IPS)
    • Ultra-low read power consumption
    • Power-On Read function
    • Built-in word-line test mode
    • Built-in bit-line test mode
    • Built-in sense amplifier test mode
    • Built-in cell margin modes for programming verification